Memory Adressing/Allocation/Relocation TRIZ Cases
- Memory Controller Access Scheme Optimization for Faster Random Access
Precomputed access schemes reduce random-memory latency and controller overhead.
- Snoop Filter Segmentation for Precise Scalable Cache Tracking
Grouped snoop filter instances scale cache tracking without sacrificing presence-vector precision or address capability.
- Memory System Thermal Voltage Model Selection for Lower Latency and Power Use
The memory system shifts from broad to temperature-matched voltage models, reducing latency and power consumption during operation.
- QLC Memory Programming With Separate Sense Times for Vt Width Control
This case uses stage- and state-dependent sense times in QLC foggy-fine programming to improve efficiency and Vt width control.
- Neural Network Processing With Dedicated and Shared Storage Routing
A control element selects dedicated or shared storage for graph connections, improving transfer efficiency and freeing CPU resources.
- Host-Aware Data Storage Resource Allocation for Endurance
A storage controller detects host capabilities, then adjusts resources and programming parameters to reduce errors and extend endurance.
- NAND Memory Read-Voltage Adjustment for Charge-Drift Accuracy
This memory case uses boundary voltages and bidirectional read-voltage adjustment to limit bit errors from charge and temperature shifts.
- Memory Device Channel Modulation to Reduce Signal Interference
A memory device uses larger-range data signaling and smaller-range error detection signaling to limit interference during communication.
- Memory Latch-to-FIFO Prefetch for Faster Read Data Fetching
This memory case uses a FIFO to prefetch latch data during reads, reducing sequential waiting and improving fetch speed.
- Multichannel Memory with Off-Chip Scratchpads for Capacity Limits
This architecture combines on-chip scratchpads with multichannel off-chip DRAM to ease capacity limits and reduce energy use.
- Bijective Matrix Address Scrambling in Galois Fields for Memory Security
Seed-selected bijective matrices scramble logical addresses in memory, strengthening protection while preserving reversible physical access.
- Static Output-Data Memory Allocation for Microcontroller Execution
A one-time execution analysis assigns output data to reusable fixed memory areas, reducing memory needs and allocation latency.
- Host-Controlled AI Weight Loading Across Memory Channels
A host aligns lightweight AI weight files to device channels, enabling parallel loading and faster data transfer.
- SRAM Read Circuitry With Blast-Mode Column Multiplexing
Blast-mode SRAM reads use column multiplexing and one sense amplifier to cut clock cycles.
- Read-Modify-Write Manager With Arithmetic Pipeline for Coherent Updates
An arithmetic-pipeline RMW manager enables coherent shared-memory updates without firmware locks.
- Memory Access Metadata Mapping for Persistent CXL Operations
Metadata actions move, copy, or reset alongside memory access operations, preserving heat maps and prefetch history.
- Memory Read Control Circuit with Adaptive Voltage Retry Sequences
This case uses stored read-voltage tables and retry history to adapt sequences, improving read efficiency as memory aging changes.
- Non-Volatile Memory Read Voltage Control with LLR Feedback
Hard and soft bit reads guide LLR-based shift adjustment, improving data accuracy despite threshold voltage variation.
- Non-Volatile Memory Sub-Block Layout for Simpler Erase Operations
Vertically stacked sub-blocks use normal and reserved regions to reduce erase complexity and resource demands in high-capacity memory.
- Secure SoC Version Directory for External Memory Rollback Detection
A secure SoC version directory detects rollback attacks in external memory.
- Mobile Edge Cache Prediction with Federated Learning and Attention Aggregation
Clustered user selection and attention-weighted aggregation predict mobile content popularity for proactive edge caching.
- Disaggregated Memory Pooling With Dynamic Address Mapping
Software-programmed memory pooling maps host addresses to non-contiguous local regions, improving flexibility and access latency.
- Memory System Power Policy Matching for Host Compatibility
Host capability identifiers let memory systems adjust power policies, balancing storage performance with compatibility across devices.
- Data Processing Memory Segmentation for Real-Time Access
A shared first memory area and CPU-only second area reduce resource competition while preserving real-time data access.
- Analog Matrix Multiplier Fabric With Reinforcement-Learned Compute Routing
Reinforcement learning routes analog compute blocks to cut matrix multiplication latency and power.