Memory Latch-to-FIFO Prefetch for Faster Read Data Fetching
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Solution Overview
Problem
Existing memory systems, particularly those utilizing NAND flash memory, face challenges in enhancing operation speed during data fetching operations.
Innovation Solution
A memory system incorporating a first chip with a first plane and a first input/output circuit, featuring a first FIFO circuit capable of fetching read data from a first latch circuit during a read operation, controlled by a controller that issues commands for data fetching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data fetching is performed sequentially after read operation completion, then data transfer accuracy is maintained, but operation speed deteriorates
Solution Approach 1:
The patent implements preliminary action by enabling the FIFO circuit to fetch data from the latch circuit during the read operation period itself, rather than waiting for the read operation to complete. The controller issues a fetch command that overlaps with the read operation timing, allowing data to be transferred in advance while the read operation is still in progress. This eliminates the sequential waiting time and achieves parallel execution of read and fetch operations.
2Productivity
If data fetching is performed during read operation, then operation speed is enhanced, but data transfer control complexity increases
Solution Approach 1:
The patent applies universality by designing the controller to issue multiple types of commands (read commands and fetch commands) through the same command interface and control logic. The controller can selectively issue a fetch command alongside or during read operations based on system state, making the control mechanism multi-functional. This avoids adding separate dedicated control circuits for fetching while still enabling sophisticated data transfer control.
Solution Approach 2:
The FIFO circuit serves as an intermediary buffer between the latch circuit and the external interface. It receives data from the latch circuit during read operations and makes it available for external reading afterward. This intermediary structure simplifies control by decoupling the internal data transfer timing from external data output timing, allowing the controller to issue fetch commands without complex timing coordination.
3Speed
If traditional sequential data fetching is used, then control logic remains simple, but operation speed is limited
Solution Approach 1:
The patent implements continuity of useful action by ensuring that the FIFO circuit continuously operates during the read operation period to fetch data from the latch circuit. Instead of idle waiting periods, the system maintains continuous data transfer activity throughout the read operation. The fetch operation overlaps with the read operation in time, eliminating gaps and maximizing utilization of the data path throughout the entire operation duration.
Data Source
AI summary
A semiconductor memory device includes a first plane, a first input/output circuit, and a sequencer. The first plane includes a first memory cell array having a plurality of first memory cell transistors, and a first latch circuit configured to store first read data read from the first memory cell array. The first input/output circuit includes a first FIFO circuit configured to fetch the first read data from the first latch circuit. The sequencer is configured to control the first plane and the first input/output circuit based on a command transmitted from an external controller. The sequencer is configured to execute a prefetch operation for fetching the first read data from the first latch circuit into the first FIFO circuit within a period in which a read operation is executed in the first plane.