Read-Modify-Write Manager With Arithmetic Pipeline for Coherent Updates
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Solution Overview
Problem
Existing network-connected integrated circuits face challenges in efficiently updating shared network statistics values without locking the memory, which consumes device resources and complicates firmware or software programs.
Innovation Solution
A read-modify-write (RMW) manager is implemented, comprising a controller, arithmetic pipeline, and write pipeline, which processes update requests to shared memory locations without locking, ensuring coherency and reducing resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory locking is used to ensure coherency during updates, then data consistency is improved, but device resources are consumed and firmware complexity increases
Solution Approach 1:
The patent introduces an intermediary RMW manager component that sits between the processor cores and the shared memory. This manager handles the read-modify-write operations and coherency maintenance, freeing the firmware from implementing complex locking protocols. The RMW manager acts as a mediator that translates simple update requests from firmware into coordinated memory operations that maintain coherency without requiring firmware to manage locks directly.
Solution Approach 2:
The system implements self-service through the RMW manager that automatically manages the locking and coherency protocols. When a processor core needs to update shared memory, it simply issues an update request to the RMW manager, which then handles the entire read-modify-write sequence, acquires necessary locks, ensures coherency, and writes back the updated value. This self-service mechanism eliminates the need for firmware to implement complex locking logic while maintaining data consistency.
2Reliability
If memory locking is used to ensure coherency during updates, then data consistency is improved, but device area increases
Solution Approach 1:
The RMW manager serves as an intermediary that consolidates the locking and coherency management functionality in a dedicated component rather than distributing lock management across multiple firmware modules. This centralized approach reduces the overall device area by eliminating redundant lock management logic and associated hardware resources that would be needed if each firmware component implemented its own locking mechanisms.
Solution Approach 2:
The RMW manager is designed as a universal component that handles all read-modify-write operations for shared memory across multiple processor cores. This multi-functional approach consolidates what would otherwise require separate locking mechanisms and coherency management logic for each core or firmware module, reducing the total device area by sharing common hardware resources for lock management and coherency maintenance.
3Productivity
If concurrent updates to shared memory are allowed, then processing efficiency is improved, but maintaining coherency becomes more difficult
Solution Approach 1:
The RMW manager acts as an intermediary that enables concurrent updates from multiple processor cores while maintaining coherency. It receives update requests from multiple cores simultaneously, queues them appropriately, and processes them in an order that maintains memory consistency. This mediation allows high concurrency while the RMW manager handles the complexity of coherency management, keeping the firmware simple.
Solution Approach 2:
The system enables self-service concurrent updates where processor cores can independently issue update requests to shared memory without coordinating with each other. The RMW manager automatically manages the concurrency control and coherency maintenance, allowing multiple cores to update shared memory concurrently while the RMW manager ensures that updates are applied in a coherent manner without requiring cores to implement complex synchronization logic.
Data Source
AI summary
In described examples, a device includes first and second memories, an arithmetic pipeline, a write pipeline, and a controller. Update requests include an ADD value and a memory location indicator of the second memory. The first memory receives and stores a first update request at a tail memory location. A read of the second memory is controlled responsive to a read of a second memory location indicator of a second update request from an intermediate memory location of the first memory, and a responsive read data is stored at the intermediate memory location. A third update request and a read data are read from a head memory location of the first memory, and provided to the arithmetic pipeline. The arithmetic pipeline adds the corresponding ADD value and read data to generate a result, which is provided to the write pipeline. The write pipeline responsively generates a write transaction.