SRAM Read Circuitry With Blast-Mode Column Multiplexing
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Solution Overview
Problem
The speed of data access in static random access memory (SRAM) is limited by the time required for read and write operations, contributing to higher latencies and reducing the processing unit's performance.
Innovation Solution
Implementing a 'blast mode' read operation that allows multiple words to be read or written across multiple columns in fewer clock cycles using a column read-out multiplexer and a single sense amplifier, along with optimized precharge and sense amplifier control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional read operation is used to read data from SRAM, then data can be read accurately, but the read operation takes multiple clock cycles and limits processing speed
Solution Approach 1:
The patent combines multiple column readout operations into a single blast read operation. Instead of reading columns individually, the system uses a column readout multiplexer to connect multiple columns to a single sense amplifier, allowing parallel reading of multiple bits in one operation. This merging of operations directly reduces read latency and increases data read speed.
Solution Approach 2:
The patent segments the readout process by introducing a column readout multiplexer that can selectively connect different columns to the sense amplifier. This segmentation allows the system to read multiple columns in parallel during a single blast read operation, improving throughput while maintaining accurate data retrieval for each column.
2Productivity
If multiple columns are read out simultaneously using blast mode, then throughput increases, but the circuit complexity increases due to additional multiplexer control logic
Solution Approach 1:
The column readout multiplexer serves multiple functions: it selects which columns are connected to the sense amplifier, controls the timing of column readout operations, and enables both single-column and multi-column blast read modes. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity while achieving high throughput.
3Area of stationary object
If a single sense amplifier is used for multiple columns, then area and leakage are reduced, but the sense amplifier must be rapidly switched between columns requiring precise control
Solution Approach 1:
The control circuit performs preliminary actions by pre-charging the sense amplifier and preparing the column readout multiplexer before each blast read operation. The control signals are generated in advance to ensure the sense amplifier is ready to receive data from any selected column, reducing the complexity of rapid switching during the actual read operation.
Solution Approach 2:
The control circuit uses feedback mechanisms to monitor the state of the sense amplifier and column readout multiplexer, adjusting control signals accordingly. This feedback ensures precise timing and proper switching between columns, maintaining accurate data reading while using a single sense amplifier for multiple columns.
Data Source
AI summary
A read circuitry for memory includes a column read-out multiplexer (MUX) coupled to a set of columns of the memory, wherein the column read-out MUX receives a column select signal from a control circuit to output a corresponding column output from the set of columns; and a single sense amplifier coupled to receive the corresponding column output of the column read-out MUX.