Non-Volatile Memory Sub-Block Layout for Simpler Erase Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face challenges with increasing capacity and size, leading to complex erase operations, resource requirements, and management difficulties in garbage collection and wear leveling, which deteriorate performance.
Innovation Solution
A non-volatile memory device with sub-blocks of different sizes arranged vertically, including normal and reserved regions, managed by a storage controller to optimize erase operations and reduce address mapping complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on a substrate is increased to achieve higher capacity, then the storage capacity is improved, but the size of the memory block increases and the complexity of erase operations increases
Solution Approach 1:
The memory block is divided into multiple sub-blocks, each with a manageable number of word lines. This segmentation allows erase operations to be performed on individual sub-blocks rather than the entire large block, reducing the complexity and resource requirements of each erase operation while maintaining high overall storage capacity through vertical stacking of multiple sub-blocks.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking architecture. By stacking multiple sub-blocks vertically above the substrate, the system achieves higher storage capacity without proportionally increasing the footprint area, and enables independent erase operations on each sub-block layer.
2Quantity of substance
If the size of the memory block is increased to achieve higher capacity, then the storage capacity is improved, but the resources required to perform erase operations on each sub-block increase
Solution Approach 1:
By segmenting the large memory block into smaller sub-blocks, each erase operation affects only a portion of the total capacity. This reduces the energy and computational resources required per erase operation compared to erasing the entire large block at once, while the aggregate capacity remains high due to the combined size of all sub-blocks.
3Quantity of substance
If sub-blocks of different sizes are used to optimize memory management, then the storage capacity is improved, but the complexity of managing garbage collection and wear leveling increases
Solution Approach 1:
Different sub-blocks are designed with different sizes tailored to specific functional requirements. Some sub-blocks are optimized for sequential writes, others for random access, and some for wear leveling. This local optimization allows each sub-block to excel at its specific function while the overall system achieves high capacity and improved performance through differentiated design.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device includes a plurality of sub-blocks having different sizes and arranged in a vertical direction above a substrate, wherein a first sub-block and a second sub-block among the plurality of sub-blocks each includes a normal region and a reserved region configured to store data after at least some pieces of data stored in the normal region are invalidated, a third sub-block among the plurality of sub-blocks has a smallest size among the different sizes, and a size of the normal region of each of the first sub-block and the second sub-block is equal to or less than the size of the third sub-block.