Discrete 3D Processor With Split Memory and Logic Dies
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Solution Overview
Problem
Conventional processors face inefficiencies due to limited computational density and complexity, inability to perform non-arithmetic functions, and high costs associated with integrating 2-D and 3-D circuits, leading to slow performance in mathematical computing, computer simulation, pattern processing, and neural networks.
Innovation Solution
A discrete 3-D processor is designed with 2-D and 3-D circuits partitioned into separate dice, allowing for optimized manufacturing and performance of peripheral circuits and logic components, enhancing array efficiency, reducing costs, and enabling flexible functionalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 2-D and 3-D circuits are integrated on the same die, then functional integration is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The processor is divided into two separate dies: a first die containing the 3-D memory array and a second die containing the logic circuit and peripheral circuits. This segmentation allows each die to be optimized for its specific function and manufactured using appropriate processes, reducing overall manufacturing complexity while maintaining functional integration through die stacking.
Solution Approach 2:
The peripheral circuits are extracted from the first die (3-D memory array) and placed on the second die (logic circuit die). This extraction simplifies the first die to contain only the memory array, improving array efficiency and reducing manufacturing complexity, while the second die handles all peripheral functions.
2Adaptability or versatility
If 2-D and 3-D circuits are integrated on the same die, then functional integration is achieved, but manufacturing cost increases
Solution Approach 1:
By segmenting the processor into separate dies for 3-D memory and logic circuits, each die can be manufactured using optimized processes appropriate to its function, reducing overall manufacturing cost while maintaining functional integration through die stacking.
Solution Approach 2:
Extracting peripheral circuits from the first die reduces the complexity and cost of manufacturing the 3-D memory array die, allowing it to be produced more efficiently while peripheral functions are implemented on the second die.
3Ease of manufacture
If logic circuit and memory circuit are disposed on the same plane, then conventional 2-D integration is achieved, but computational density is limited
Solution Approach 1:
The invention transitions from 2-D planar integration to 3-D vertical stacking, with the first die (3-D memory array) stacked above the second die (logic circuit). This dimensional change dramatically increases computational density by utilizing the vertical space above the logic circuit, allowing memory and processing to be closely integrated in three dimensions.
4Device complexity
If processor and external memory are separated, then von Neumann architecture is achieved, but data transfer bandwidth is limited
Solution Approach 1:
The invention merges the memory function and processing function into a single integrated processor unit through 3-D stacking. The 3-D memory array on the first die is directly coupled to the logic circuit on the second die, creating a unified processor that combines both functions and enables high-bandwidth data transfer between memory and processing units.
Data Source
AI summary
A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays and on-die peripheral-circuit components of the memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The off-die peripheral-circuit components have a better performance than the on-die peripheral-circuit components.