Discrete 3-D Processor Architecture for Neural Network Computing
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Solution Overview
Problem
Conventional processors, based on two-dimensional integration and von Neumann architecture, face inefficiencies in mathematical computing, computer simulation, pattern processing, and neural networks due to limited internal memory, narrow data transfer bandwidth, and inability to implement non-arithmetic functions effectively.
Innovation Solution
A discrete 3-D processor design that de-integrates 2-D and 3-D circuits, partitioning them into separate dice for optimized performance, featuring a memory die with multiple functional levels and a logic die with a single functional level, allowing for increased computational density and flexibility by using memory-based computation with three-dimensional memory arrays and arithmetic logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional two-dimensional integration is used to dispose logic circuit and memory circuit on the same plane, then device complexity is reduced and manufacturing is easier, but computational density is limited and processing power is insufficient
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integration by stacking multiple functional layers vertically. The processor includes a first substrate with logic circuit, a second substrate with memory circuit, and additional functional layers stacked above, thereby increasing computational density while maintaining manufacturing feasibility through modular layering.
Solution Approach 2:
The processor is divided into separate functional modules stacked in three dimensions: logic circuit layer, memory circuit layer, input/output interface layer, and calculation unit layer. Each layer is independently designed and manufactured, then integrated through vertical stacking, resolving the contradiction between manufacturing ease and computational density.
2Device complexity
If von Neumann architecture with physically separated processor and memory is used, then device complexity is reduced, but data transfer bandwidth is limited and computing efficiency deteriorates
Solution Approach 1:
The patent merges processor and memory circuits into a single integrated three-dimensional structure. The logic circuit and memory circuit are disposed on different substrates that are vertically stacked and electrically connected, enabling high-speed data transfer while maintaining functional separation. This resolves the contradiction by combining the benefits of both separation and integration.
Solution Approach 2:
By transitioning to three-dimensional integration, the patent reduces the physical distance between logic and memory circuits through vertical stacking. The inter-substrate connections provide high-bandwidth data transfer paths, increasing data transfer bandwidth while keeping the overall device footprint small and complexity manageable.
3Productivity
If arithmetic logic unit is used for mathematical computing, then basic arithmetic operations are efficient, but non-arithmetic functions cannot be implemented effectively
Solution Approach 1:
The patent implements a multi-functional processor that can perform both arithmetic operations and non-arithmetic functions. The logic circuit is designed to execute arithmetic operations efficiently, while the integrated memory circuit stores lookup tables for non-arithmetic functions. The system can dynamically switch between computational modes, achieving versatility without sacrificing arithmetic performance.
Solution Approach 2:
The processor separates arithmetic logic functions from non-arithmetic function implementation. The logic circuit handles arithmetic operations, while the memory circuit stores pre-computed values for non-arithmetic functions. This segmentation allows each component to be optimized for its specific function while working together to provide comprehensive computational capability.
4Device complexity
If limited internal memory is provided on processor die, then device complexity is reduced, but computing efficiency for large data processing deteriorates
Solution Approach 1:
The patent uses three-dimensional stacking to dramatically increase the memory capacity on the processor die. Multiple memory layers are stacked vertically above the logic circuit substrate, providing large internal memory capacity while maintaining a compact footprint. This resolves the contradiction by increasing memory capacity without proportionally increasing device complexity.
Solution Approach 2:
The processor integrates large capacity memory circuit directly with the logic circuit through vertical stacking. The memory circuit is disposed on a separate substrate that is bonded to the logic circuit substrate, creating a unified high-performance computing package with large internal memory capacity that improves computing efficiency for large data processing.
Data Source
AI summary
A discrete 3-D processor comprises first and second dice. The first die comprises three-dimensional memory (3D-M) arrays, whereas the second die comprises logic circuits and at least an off-die peripheral-circuit component of the 3D-M array(s). The first die does not comprise the off-die peripheral-circuit component. The first and second dice are communicatively coupled by a plurality of inter-die connections. The preferred discrete 3-D processor can be applied to mathematical computing, computer simulation, configurable gate array, pattern processing and neural network.