3D Memory Devices With Discrete Charge Trapping Layers
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Solution Overview
Problem
The challenge in scaling up 3D NAND flash memory devices is the degradation of performance due to the continuous charge trapping layer, which leads to charge spreading and loss, limiting vertical scale-up, and increasing fabrication complexity with discrete charge trapping layers.
Innovation Solution
The implementation of discrete charge trapping layers at different levels above an inverted 'T' or double-sided staircase-shaped gate electrode, along with corresponding channel layers, mitigates the charge spreading effect without increasing fabrication complexity, allowing for vertical scaling of 3D memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a continuous charge trapping layer is used, then the fabrication process is simpler, but charge spreading and loss occur leading to performance degradation
Solution Approach 1:
The continuous charge trapping layer is divided into multiple discrete charge trapping layers positioned at different vertical levels. Each discrete layer is independently formed and controlled, preventing charge spreading between layers while maintaining fabrication feasibility through sequential deposition processes
2Reliability
If discrete charge trapping layers are used, then charge spreading is reduced improving performance, but fabrication complexity increases
Solution Approach 1:
The charge trapping functionality is extended from a single horizontal plane to multiple vertical levels. Discrete charge trapping layers are positioned at different heights above the gate electrode, utilizing the vertical dimension to separate charge confinement zones while maintaining a streamlined fabrication process
3Productivity
If vertical scaling is increased to improve memory density, then more memory cells are achieved, but charge spreading and performance degradation worsen
Solution Approach 1:
The vertically stacked memory structure is segmented into multiple decks, each with its own discrete charge trapping layers. This segmentation allows independent charge confinement in each deck, preventing vertical charge spreading while enabling increased memory density through additional stacked layers
Solution Approach 2:
Memory capacity is increased by utilizing the vertical dimension with multiple stacked memory decks rather than expanding laterally. Each deck operates independently with its own charge trapping layers, maintaining performance while achieving higher density through vertical stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of 3D memory devices by reducing charge spreading and loss, enabling further vertical scaling without increasing fabrication complexity, thereby improving memory density.
Implementation Method 1
a plurality of discrete charge trapping layers disposed at different levels are formed on the first blocking layer
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a plurality of memory decks stacked above the substrate. Each of the memory decks includes a gate electrode, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, a channel layer on the tunneling layer, and an inter-deck dielectric layer on the channel layer. The plurality of charge trapping layers are discrete and disposed at different levels. A top surface of the inter-deck dielectric layer is nominally flat. The gate electrode of another one of the memory decks immediately above the memory deck is disposed on the top surface of the inter-deck dielectric layer.