Discrete Charge Trapping Layers in 3D Memory Devices
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Solution Overview
Problem
The challenge in 3D NAND flash memory devices is the degradation of performance due to the continuous charge trapping layer, which leads to charge spreading and loss, limiting vertical scale-up and increasing fabrication complexity.
Innovation Solution
The implementation of discrete charge trapping layers at different levels, formed using an inverted 'T' or double-sided staircase-shaped gate electrode, mitigates the charge spreading effect without increasing fabrication complexity, allowing for vertical scaling of 3D memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a continuous charge trapping layer is used, then the fabrication process is simple, but charge spreading and loss occur leading to performance degradation
Solution Approach 1:
The continuous charge trapping layer is divided into multiple discrete charge trapping layers positioned at different vertical levels. Each discrete layer is separated by tunneling layers and channel layers, preventing charge spreading between layers while maintaining individual charge storage capability. This segmentation resolves the contradiction by preserving charge retention performance through isolation while managing fabrication complexity through systematic layering.
Solution Approach 2:
The charge trapping structure transitions from a two-dimensional continuous layer to a three-dimensional stacked architecture with discrete layers at different vertical levels. This dimensional change allows charge to be trapped at multiple heights, reducing lateral spreading while enabling vertical stacking for increased density without proportionally increasing fabrication complexity.
2Quantity of substance
If vertical scaling is pursued to increase memory density, then more memory cells can be packed, but fabrication complexity increases
Solution Approach 1:
Multiple discrete charge trapping layers are nested vertically within a stacked structure, with each layer containing memory cells. The tunneling layers and channel layers are nested between the charge trapping layers, creating a compact vertical arrangement. This nesting enables high memory density by packing multiple functional layers in the vertical dimension without proportionally increasing lateral fabrication complexity.
Solution Approach 2:
Memory density is increased by transitioning from lateral expansion to vertical stacking. Multiple discrete charge trapping layers are positioned at different heights, allowing memory cells to be arranged in three dimensions. This vertical scaling approach increases the quantity of memory cells without requiring proportional increases in lateral fabrication complexity, as the same fabrication processes can be applied repeatedly in the vertical direction.
3Reliability
If discrete charge trapping layers are implemented, then charge spreading is reduced improving performance, but fabrication complexity increases
Solution Approach 1:
Multiple discrete charge trapping layers are combined into a unified stacked structure with systematic positioning. The tunneling layers and channel layers serve as common structural elements that integrate the discrete charge trapping layers into a cohesive device. This merging approach maintains charge retention performance through discrete layer isolation while managing fabrication complexity by treating the structure as an integrated stack rather than separate components.
Solution Approach 2:
The gate electrode is formed with a preliminary inverted T-shape or double-sided staircase configuration that pre-establishes the spatial framework for subsequent discrete charge trapping layers. This preliminary structuring guides the precise positioning of discrete layers at different levels, reducing fabrication complexity by providing a pre-defined template rather than requiring complex alignment procedures for each layer.
Data Source
AI summary
A method for forming a 3D memory device is disclosed. A gate electrode having an inverted âTâ shape is formed above a substrate. A continuous blocking layer is formed on the gate electrode. A continuous charge trapping layer is formed on the blocking layer. A first thickness of a first part of the charge trapping layer extending laterally is greater than a second thickness of a second part of the charge trapping layer extending vertically. The second part of the charge trapping layer extending vertically is removed to form a plurality of discrete charge trapping layers disposed at different levels on the blocking layer from the first part of the charge trapping layer extending laterally. A continuous tunneling layer is formed on the discrete charge trapping layers. A continuous channel layer is formed on the tunneling layer.