Solid-State Devices TRIZ Cases

A silicon carbide gate oxide film incorporates steplike portions at the edge to relax electric field concentration.

Segmented charge trapping layers prevent lateral charge spreading and loss, enabling vertical scaling of 3D NAND flash memory devices.

Vertical conducting portions decouple electrode arrangement from electrical connection, resolving design flexibility constraints in bonding electrodes.

Air regions in stuffed material reduce light loss and cross-talk by shortening the optical path.

Stacked avalanche diodes place pulse shaping circuits on the first chip to reduce output node time constants and improve photon counting accuracy.

A solid-state imaging device positions vertical signal lines below pixel electrodes to reduce capacitive coupling between unit cells.

An inclined insulating layer wall supports nanoscale light emitting structures to reduce stress differences during growth.

An OLED structure uses a PN junction and high impedance conductive layer to form a resistive divider that adjusts cathode potential.

A thin film transistor substrate uses diffusion barriers between metal layers to prevent atom migration.

Segmented detection channels resolve contaminants with similar density by analyzing coherent and Compton scattering patterns.

An organic electronic multi-sensor fuses an ionic electrolyte with a semiconductor polymer to detect gases, light, and temperature changes.

A manufacturing method for thin film transistor array substrates uses three masks to form gate electrodes, semiconductor layers, and transparent conduction films.

Segmented InAlSb absorbers block majority carriers to resolve dark current trade-offs.

Separating the gate electrode into the charge transport layer simplifies fabrication while maintaining effective current control and low operational voltage.

An open region in the sensing electrode reduces parasitic capacitance caused by pixel definition layer variations, improving touch sensitivity.

A segmented anode structure with dielectric isolation pinches off the two-dimensional electron gas layer in reverse bias mode.

Thick transparent metal oxide electrode layer adjusts optical thickness to align with RGB wavelengths.

A liquid crystal display uses a slit electrode and photo-aligned layer to orient molecules vertically.

Selective salicide process reduces wordline resistance without causing junction defects or leakage.

A resistive random access memory device uses a nickel oxide layer doped with iron, cobalt, and tin elements to achieve stable resistance switching.

A third electrode covers a contact hole to electrically connect first and second electrodes within an inorganic insulating film stack.

Integrating peripheral circuitry with phase change cells on amorphous substrates reduces manufacturing costs while maintaining device reliability.

A semiconductor gate structure design featuring specific isolation layer arrangements to enhance electrical insulation and device reliability.

Offset-stacked semiconductor chips on a printed circuit board resolve the trade-off between data processing capacity and fabrication complexity.

A multi-layer barrier structure controls film thickness and hydrophobicity to resolve uneven distribution issues from inkjet printing.

Second electrode overlaps active layer steps to shield oxide semiconductors from hydrogen gas erosion and maintain electrical stability.

Segmenting the substrate with a blocking mask prevents edge non-uniformities from affecting central arrays, reducing center-to-edge line width deviation.

A light-emitting device package uses a body through-hole and spaced metal units to discharge heat from the upper surface.

A hybrid amplifier circuit combines a tunnel field-effect transistor with a conventional metal-oxide semiconductor field-effect transistor.

A coated organic electroluminescence device positions the light emission region on the electron transport layer side to enhance radiative recombination.

Alternating pixel rows with directional sub-pixels share mask openings to increase fabrication accuracy, resolving color mixing and jagged twill issues.

A plasma generating section cleans bonding tool tips using microplasma ejected from a nozzle aligned with the capillary center line.

A dual-gate chemical sensing field effect transistor integrates a functional layer to detect target analytes with high precision.

A light emitting device uses a transmissive layer between wavelength conversion portions to direct source light outward.

Merging multiple LED chips into a single unit eliminates complex cutting steps, boosting manufacturing yield and emission intensity.

Photopolymerized monomers create self-aligned partition walls that maintain cell gap stability and improve layer adhesion in high-definition displays.

Protrusion patterns on carrier glass enable automatic opening formation during separation, reducing impurity risks and process load.

A light transmission control layer adjusts transmittance via electrical signals to manage optical interference in display devices.

Segmented line banks with alternating gaps enable accurate inkjet application and prevent flow between adjacent cells.

Polymer brush structures with parallel oriented polymers exhibit controlled birefringence through surface-initiated ring-opening metathesis polymerization.

Capacitive coupling provides a high-frequency reference potential, resolving signal quality deterioration caused by reverse bias mismatch.

A field-effect transistor uses a paraelectric amorphous oxide passivation layer to protect the semiconductor channel.

Organic protective layer covers metal film edges in flexible display grooves.

Adjusted barrier layer thermal conductivity concentrates Joule heat to enable lower power consumption and stable switching operations.

Silicon-based buffer layers balance residual stress between inorganic and organic encapsulation films, preventing lift-off failure during bending.

An auxiliary electrode connects to the top electrode lead wire through a via hole in the thin-film encapsulation layer.

Segmented dielectric layers protect the gate electrode from dopant diffusion, decoupling threshold voltage tuning from source/drain fabrication.

Side grooves in the interlayer distribute bending stress uniformly, preventing signal line breakage and improving yield.

A dummy region at the periphery of an active matrix display unit manages scanning line coupling and pitch conversion for efficient wiring arrangement.