FET Passivation with Paraelectric Amorphous Oxide
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Solution Overview
Problem
Field-effect transistors (FETs) used in flat panel displays and other electronic devices face challenges in maintaining a stable threshold voltage due to moisture, oxygen, and hydrogen exposure, leading to reliability issues and variations in performance over time, particularly when using amorphous silicon or polycrystalline silicon semiconductors.
Innovation Solution
A field-effect transistor with a passivation layer formed from a single layer of paraelectric amorphous oxide containing an alkaline earth metal and elements like Ga, Sc, Y, or lanthanoids, combined with a gate insulating layer of Si oxides, nitrides, or oxynitrides, which helps in minimizing changes in threshold voltage during bias temperature stress tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon or polycrystalline silicon is used in the semiconductor layer, then the FET can be easily manufactured with a flat structure, but the threshold voltage changes significantly due to moisture, oxygen, and hydrogen exposure
Solution Approach 1:
The patent employs a composite material strategy by using oxide semiconductors (such as In-Ga-Zn-O) instead of conventional amorphous or polycrystalline silicon. These oxide semiconductors inherently provide better resistance to moisture, oxygen, and hydrogen while maintaining compatibility with low-temperature manufacturing processes. The composite approach combines the benefits of ease of manufacture with improved threshold voltage stability.
Solution Approach 2:
The patent implements an inert environment strategy through the use of oxide semiconductor materials that are chemically inert to moisture, oxygen, and hydrogen. The oxide semiconductor layer forms a stable structure that does not readily react with atmospheric contaminants, effectively creating an inert environment protection without requiring additional complex encapsulation layers.
2Reliability
If a passivation layer is added to suppress threshold voltage change, then the reliability improves, but the device complexity increases
Solution Approach 1:
The patent merges the semiconductor layer and passivation functions into a single oxide semiconductor layer. This layer simultaneously serves as the active semiconductor component and provides inherent protection against environmental degradation. By combining these functions, the patent eliminates the need for separate complex passivation structures while maintaining threshold voltage stability.
Solution Approach 2:
The oxide semiconductor layer provides self-service protection by inherently resisting degradation from moisture, oxygen, and hydrogen exposure. The material's chemical stability and oxide structure naturally prevent threshold voltage drift without requiring additional external passivation layers or complex protective structures.
3Speed
If oxide semiconductor is used to achieve higher carrier mobility, then the driving speed improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent changes the material parameter from conventional silicon to oxide semiconductor, which fundamentally alters the carrier mobility characteristics. This material parameter change enables higher driving speeds while the patent maintains manufacturing simplicity by using low-temperature processing techniques and simple layer structures that are compatible with existing fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a field-effect transistor with high reliability and minimal change in threshold voltage over time, enhancing the stability and performance of FETs in various electronic devices.
Implementation Method 1
the passivation layer is formed of a single layer containing a paraelectric amorphous oxide
Data Source
AI summary
A field-effect transistor including: a substrate; a passivation layer; a gate insulating layer, formed between the substrate and passivation layer; a source electrode and a drain electrode, formed to be in contact with the gate insulating layer; a semiconductor layer, formed at least between the source electrode and drain electrode and being in contact with the gate insulating layer, source electrode, and drain electrode; and a gate electrode, in contact with the gate insulating layer and facing the semiconductor layer via the gate insulating layer, wherein the passivation layer is formed of a single layer containing a paraelectric amorphous oxide containing a Group A element, an alkaline earth metal and a Group B element, at least one selected from Ga, Sc, Y, and lanthanoid, and the gate insulating layer contains at least one selected from oxides of Si, nitrides of Si, and oxynitrides of Si.