Offset-Stacked Semiconductor Chip Architecture for Area Reduction
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high capacity and performance while maintaining a reduced size, as single semiconductor chips cannot meet the required capacity due to integration limitations, necessitating multiple chips in a single package, which poses fabrication and electrical connection difficulties.
Innovation Solution
A semiconductor package design featuring multiple chip stacks offset-stacked in specific directions on a base substrate, with a printed circuit board connecting the chip stacks to the substrate, allowing for efficient electrical connections and reduced area occupation, using wire bonding and a printed circuit board to overcome process failures and pitch limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are embedded in one semiconductor package to increase capacity, then the data processing capacity is improved, but the fabrication complexity and electrical connection difficulty increase
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked chip architecture. Multiple semiconductor chips are vertically stacked on the base substrate, utilizing the vertical dimension to increase capacity while maintaining a compact footprint. This dimensional change allows multiple chips to coexist in a limited area without increasing fabrication complexity proportionally.
Solution Approach 2:
The semiconductor package is segmented into multiple independent chip stacks, each containing one or more semiconductor chips. These chip stacks are separately fabricated and then assembled on the base substrate through the printed circuit board. This segmentation allows for modular fabrication and assembly, reducing overall fabrication complexity while maintaining high data processing capacity.
2Quantity of substance
If multiple semiconductor chips are embedded in one semiconductor package to increase capacity, then the data processing capacity is improved, but the electrical connection difficulty increases
Solution Approach 1:
A printed circuit board is introduced as an intermediary component between the base substrate and the chip stacks. The printed circuit board provides standardized electrical connection interfaces, simplifying the electrical connections between multiple semiconductor chips and the base substrate. This mediator component makes the manufacturing process more manageable by providing a structured connection framework.
3Area of stationary object
If multiple chips are stacked to increase integration density, then the area occupation is reduced, but the process stability deteriorates
Solution Approach 1:
By stacking chips vertically in the third dimension, the patent achieves high integration density while maintaining a small footprint area. The vertical stacking arrangement allows multiple chips to occupy the same planar space, dramatically reducing area occupation while the structured assembly process through printed circuit boards maintains process stability.
Solution Approach 2:
The printed circuit boards are prepared in advance with predetermined electrical connection patterns and interfaces before the chip stacking assembly. This preliminary preparation of connection pathways ensures that when chips are stacked and assembled, the electrical connections are already established, improving process stability and reducing assembly complexity.
4Area of stationary object
If offset-stacking is used to reduce area occupation, then the area efficiency is improved, but the structural complexity increases
Solution Approach 1:
The patent employs offset-stacking where chip stacks are positioned asymmetrically relative to each other on the base substrate. Instead of uniform grid arrangement, chip stacks are offset in specific directions to optimize space utilization. This asymmetric arrangement improves area efficiency by reducing wasted space while the regularity of the offset pattern maintains manageable structural complexity.
Data Source
AI summary
A semiconductor package includes a base substrate; a printed circuit board disposed on the base substrate; a first chip stack disposed on the base substrate on one side of the printed circuit board, and including first semiconductor chips offset-stacked in a first offset direction facing the printed circuit board; a second chip stack disposed on the first chip stack, and including second semiconductor chips offset-stacked in a second offset direction facing away from the printed circuit board; a third chip stack disposed on the base substrate on the other side of the printed circuit board, and including third semiconductor chips offset-stacked in the second offset direction; and a fourth chip stack disposed on the third chip stack, and including fourth semiconductor chips offset-stacked in the first offset direction, wherein the second and fourth chip stacks are electrically connected with the base substrate through the printed circuit board.