Wordline Resistance Reduction in Integrated Circuit Memory Devices
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Solution Overview
Problem
In integrated circuit memory devices, the resistance of polycrystalline silicon gate pedestals increases as the devices shrink, making it difficult to achieve low resistance without additional circuit lines, and thick self-aligned silicide can cause junction defects and leakage.
Innovation Solution
A selective salicide process is used to form low-resistance wordlines by saliciding the wordlines separately from the source/drain junctions, with a process that prevents the transition metal from reacting with silicon junction areas, reducing wordline resistance while maintaining the integrity of the source/drain junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick self-aligned silicide is formed to lower wordline resistance, then wordline resistance decreases, but junction defects and leakage increase
Solution Approach 1:
The patent divides the silicidation process into two separate stages: first forming a thin salicide layer on source/drain junctions to prevent defects, then forming a thick silicide layer on wordlines to achieve low resistance. This segmentation allows each region to have the optimal silicide thickness for its specific function, resolving the contradiction between low wordline resistance and prevention of junction defects
Solution Approach 2:
The patent applies different silicide thicknesses to different regions: thin salicide (50-200 nm) on source/drain junctions to prevent leakage and defects, and thick silicide (200-500 nm) on wordlines to achieve low resistance. This local differentiation of quality allows each region to have the precise properties needed for its function
2Productivity
If device size is reduced to improve integration, then device density increases, but polycrystalline silicon resistance becomes too high
Solution Approach 1:
The patent changes the material composition parameter of the gate pedestal by forming a silicide compound (e.g., nickel silicide, cobalt silicide) on the polycrystalline silicon. This parameter change transforms the high-resistance polycrystalline silicon into a low-resistance silicide compound, enabling continued use of scaled device dimensions while maintaining acceptable resistance levels
3Reliability
If additional circuit lines are added to lower resistance, then resistance decreases, but device complexity increases
Solution Approach 1:
The patent extracts the resistance-reduction function from the circuit line structure itself by forming a silicide layer directly on the gate pedestal and wordline regions. This eliminates the need for additional external circuit lines or resistors, achieving low resistance through material modification rather than structural addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wordline resistance while minimizing defects and leakage, ensuring high-speed operation and maintaining the size and functionality of the integrated circuit memory device.
Implementation Method 1
performing a salicidation process for the columns of polycrystalline silicon to form the wordlines with low resistance
Implementation Method 2
annealed to form a silicide
Data Source
AI summary
Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.