Thin Film Transistor Array Substrate Manufacturing via Three-Mask Process
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Solution Overview
Problem
The manufacturing process of thin film transistor array substrates for liquid crystal display devices is complex and costly due to the need for multiple masking processes, which complicates the production and increases costs.
Innovation Solution
A simplified manufacturing method using three masks instead of the traditional four, where specific transmissive, semi-transmissive, and interceptive regions on the masks allow for the formation of gate electrodes, semiconductor layers, and transparent conduction films with reduced steps, enabling the creation of narrow line patterns and contact holes for improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a four-step masking process is used to form gate patterns, semiconductor patterns, protective film patterns, and transparent electrode patterns, then the manufacturing precision and pattern formation capability are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple masking processes into a single masking step by using a multi-layer structure where the gate electrode, semiconductor layer, and transparent conduction film are formed simultaneously. This merging of processes reduces the overall manufacturing complexity while maintaining the precision required for forming gate patterns, semiconductor patterns, and transparent electrode patterns.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines gate patterns, semiconductor patterns, and transparent electrode patterns all at once. This multi-functional approach eliminates the need for separate masks for each pattern type, thereby reducing device complexity in the manufacturing process while preserving manufacturing precision.
2Manufacturing precision
If multiple masking processes are used to form various patterns and contact holes, then the manufacturing precision is improved, but the loss of time and productivity decrease
Solution Approach 1:
The patent performs preliminary actions by forming the gate electrode, semiconductor layer, and transparent conduction film in a single masking step before subsequent processing. This preliminary formation of multiple layers simultaneously reduces the overall manufacturing cycle time while maintaining the precision required for contact hole formation in later steps.
Solution Approach 2:
Multiple pattern formation steps are merged into a single masking process, where gate patterns, semiconductor patterns, and transparent electrode patterns are created in one operation. This merging eliminates sequential processing time while preserving the manufacturing precision needed for accurate contact hole alignment.
3Reliability
If traditional masking processes are used to form transparent electrodes, then the manufacturing reliability is maintained, but the aperture ratio and brightness are limited
Solution Approach 1:
The patent changes the parameters of the transparent conduction film formation process by using a single masking step with controlled etching, which enables the formation of narrower transparent electrode lines (1.8-2.2 μm width). This parameter change increases the aperture ratio and brightness while maintaining manufacturing reliability through precise single-step pattern formation.
Solution Approach 2:
The invention applies local quality by creating regions with different transparent conduction film characteristics: narrow transparent electrode regions (1.8-2.2 μm) for high aperture ratio, and broader contact hole regions for proper electrical connection. This local differentiation optimizes both brightness/aperture ratio and manufacturing reliability in different areas of the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the manufacturing process by two to four steps, decreases production costs, and enhances the aperture ratio and brightness of the LCD device by forming transparent electrodes with widths of 1.8-2.2 μm, while minimizing point defects in contact holes.
Implementation Method 1
forming a first photoresist pattern on the metal layer with the use of a second mask; ashing the first photoresist pattern to form a second photoresist pattern
Implementation Method 2
the third mask includes transmissive regions transmitting lights, semi-transmissive regions partially transmitting and intercepting the lights, and interceptive regions intercepting the lights
Implementation Method 3
the third mask includes transmissive regions transmitting lights, semi-transmissive regions partially transmitting and intercepting the lights, and interceptive regions intercepting the lights
Implementation Method 4
ashing the first photoresist pattern to form a second photoresist pattern, and forming patterns for data pads, data lines, and thin film transistors with the use of the second photoresist pattern
Data Source
AI summary
A simplified method of manufacturing a thin film transistor array substrate is disclosed. The method includes: forming gate electrodes, gate lines and gate pads on a substrate with the use of a first mask; forming a gate insulation film, a semiconductor layer, and a metal layer on the substrate; forming a first photoresist pattern on the metal layer with the use of a second mask; forming first contact holes for the gate pads with the use of the first photoresist pattern; forming a second photoresist pattern, and providing patterns for data pads, data lines, and thin film transistors with the use of the second photoresist pattern; providing a third photoresist pattern, and forming contact holes for source/drain electrodes and second contact holes the gate pads with the use of the third photoresist pattern; forming a protective film on the substrate and providing a fourth photoresist pattern on the protective film with the use of a third mask; forming third contact holes for the gate pads, contact holes for the data pads, gate lines, and drain electrodes, and contact holes for pixel electrodes, with the use of the fourth photoresist pattern; and forming a transparent conduction film on the fourth photoresist pattern having the contact holes.