Dished Inner Spacer Geometry for GAA Source/Drain Strain
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Solution Overview
Problem
Existing fabrication of GAA transistors introduces new challenges to the semiconductor manufacturing process and leads to associated device reliability concerns, particularly in the formation of GAA transistors, which have not been entirely satisfactory in all respects.
Innovation Solution
A method involving a dished inner spacer profile is introduced to increase the volume of the source/drain feature in GAA transistors, enhancing strain induction in semiconductor channel layers by forming a dish-like region along the lateral surface of the inner spacer during the inner spacer etch-back process, using a wet or dry etch process, or a combination thereof, to improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication techniques are used for GAA transistors, then manufacturing process complexity increases, but device reliability and performance remain unsatisfactory
Solution Approach 1:
The patent modifies the inner spacer geometry by introducing a dished profile with a recessed portion, changing the shape parameter from a simple rectangular cross-section to a complex three-dimensional structure. This geometric parameter change increases the source/drain feature volume and enhances strain induction in the semiconductor channel layer, thereby improving device reliability and performance while managing manufacturing complexity through a systematic fabrication process.
2Reliability
If the source/drain feature volume is increased to enhance strain induction, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a preliminary action approach by forming the dished inner spacer profile before creating the source/drain features. The inner spacer with its recessed portion is fabricated in advance, and subsequent deposition and etching processes build the source/drain features upon this pre-formed structure. This preliminary formation of the spacer with optimized geometry allows for better control over the final source/drain feature volume and strain characteristics, while the systematic multi-step process manages precision requirements.
Solution Approach 2:
The dished inner spacer acts as an intermediary structure that mediates between the gate structure and the source/drain features. By incorporating a recessed portion in the inner spacer, the patent creates an intermediate volume that can accommodate larger source/drain features and enhance strain induction. This intermediary structure with its specific three-dimensional geometry serves as a mediator to achieve the desired device performance while providing a controlled framework for subsequent manufacturing steps.
3Volume of moving object
If inner spacer material is removed from sidewalls to form dish-like region, then source/drain feature volume increases, but manufacturing process steps increase
Solution Approach 1:
The patent applies segmentation by dividing the inner spacer structure into distinct regions: a top surface, sidewalls, and a recessed portion forming the dish-like profile. The fabrication process correspondsingly segments the manufacturing steps into sequential operations: depositing inner spacer material, selectively removing material from sidewalls to create the recessed portion, and forming the final source/drain features. This segmentation of the structure and process allows for controlled creation of the dished profile, increasing source/drain feature volume while managing process complexity through systematic step-by-step execution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased volume of the source/drain feature enhances strain induction in semiconductor channel layers, leading to improved device performance and reliability of GAA transistors.
Implementation Method 1
using a wet or dry etch process, or a combination thereof
Implementation Method 2
using a wet or dry etch process, or a combination thereof
Implementation Method 3
enhancing strain induction in semiconductor channel layers
Data Source
AI summary
A method of fabricating a device includes providing a fin having a stack of epitaxial layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. A source/drain etch process is performed to remove portions of the stack of epitaxial layers in source/drain regions to form trenches that expose lateral surfaces of the stack of epitaxial layers. A dummy layer recess process is performed to laterally etch the plurality of dummy layers to form recesses along sidewalls of the trenches. An inner spacer material is deposited along sidewalls of the trenches and within the recesses. An inner spacer etch-back process is performed to remove the inner spacer material from the sidewalls of the trenches and to remove a portion of the inner spacer material from within the recesses to form inner spacers having a dish-like region along lateral surfaces of the inner spacers.