Display Peripheral Circuit Interval Optimization for ESD Robustness
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Solution Overview
Problem
The design of display devices faces challenges in optimizing the layout of peripheral electronic circuits to enhance electrostatic discharge (ESD) robustness, particularly in non-rectangular displays where available space is limited and wiring configurations affect the functionality and layout of ESD protection circuits.
Innovation Solution
The display device incorporates a substrate with a non-rectangular display region and a peripheral region, featuring distinct intervals between electronic circuits, where the second interval between adjacent second electronic circuits is narrower than the first interval between adjacent first electronic circuits, allowing for optimized layout and enhanced ESD protection by distributing ESD current more uniformly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are provided in the peripheral region, then ESD robustness is improved, but the layout and function of the circuits are affected by various wirings
Solution Approach 1:
The patent applies local quality by differentiating the interval widths between adjacent electronic circuits based on their location and function. Specifically, different interval widths are used in different regions of the peripheral circuit area, allowing optimization of ESD protection in certain areas while accommodating wiring requirements in other areas. This localized differentiation resolves the contradiction by making the layout adaptable to both ESD protection needs and wiring constraints.
Solution Approach 2:
The patent changes the spatial parameter of interval width between electronic circuits to optimize both ESD protection and wiring layout. By adjusting the interval width parameter differently in different regions, the patent achieves improved ESD robustness while maintaining wiring functionality, thus resolving the contradiction between reliability and device complexity.
2Ease of manufacture
If uniform intervals are used between electronic circuits, then layout simplicity is maintained, but ESD current distribution is suboptimal
Solution Approach 1:
The patent implements local quality by applying different interval widths in different regions of the electronic circuit array. This allows the layout to maintain simplicity in terms of systematic design while achieving optimized ESD current distribution through localized variations in interval spacing. The non-uniform intervals are strategically placed to improve ESD protection effectiveness without significantly complicating the overall manufacturing process.
3Area of stationary object
If narrower intervals are used between electronic circuits, then space utilization is improved, but electrical coupling capability increases which may affect ESD current diversion
Solution Approach 1:
The patent applies local quality by using different interval widths in different regions. Narrower intervals are used in areas where space utilization is critical, while wider intervals are maintained in regions where ESD current diversion is prioritized. This localized differentiation allows the patent to simultaneously achieve good space utilization and effective ESD protection by optimizing each region for its primary function.
Solution Approach 2:
The patent segments the peripheral circuit area into different regions with different interval characteristics. This segmentation allows independent optimization of space utilization in some segments and ESD current diversion capability in other segments, resolving the contradiction between these two competing requirements through spatial division of functions.
Data Source
AI summary
A display device that includes a substrate having a display region and an adjacent peripheral region is provided, including; a plurality of sub-pixels provided within the display region; a plurality of data lines electrically connected to the sub-pixels; and a first electronic circuit group and a second electronic circuit group provided in the peripheral region, connected to the corresponding data lines. The first electronic circuit group includes a plurality of first electronic circuits, and the second electronic circuit group includes a plurality of second electronic circuits. Two adjacent first electronic circuits are arranged with a first interval therebetween, and the first interval has a first width. Two adjacent second electronic circuits are arranged with a second interval therebetween, and the second interval has a second width. The first width and the second width are different.