Transistor TRIZ Cases

A Schottky diode anode encircled by a p-type region reduces reverse leakage current.

Selective germanium diffusion into silicon nanowires creates mixed channels, simplifying fabrication while minimizing short-channel effects.

A metal oxide semiconductor memory circuit uses Joule heating to switch resistance states for low power data storage.

A planar double gate semiconductor device uses high-k dielectric layers to form a thicker channel and reduce bias voltage.

A photosensor design positions output signal lines away from voltage wiring to minimize parasitic capacitance.

An FD-SOI semiconductor device applies body bias voltages to well contacts for dynamic threshold voltage adjustment.

A semiconductor component with a trench gate structure and separate field plate trench reduces switching losses and manufacturing complexity.

A thin film transistor device uses distinct crystallization processes to achieve tailored electrical characteristics for pixel and peripheral regions.

Orthohexagonal capacitor arrangement increases capacitance by displacing centers from signal line intersections.

Aspect ratio dependent etching creates semiconductor pillars with controlled lateral dimensions, reducing contact resistance in DRAM devices.

A TFT backplate structure uses distinct gate isolation layers for switch and drive transistors.

Fabricating high-density capacitors in deeper substrate trenches alongside shallower vias reduces manufacturing costs while enabling efficient RF decoupling.

A semiconductor storage node electrode includes a step on the top sub-electrode adjacent to the bottom sub-electrode.

Segmented oxide and polysilicon layers resolve the trade-off between uniformity and electron mobility in OLED displays through composite material integration.

Different interval widths between adjacent electronic circuits in the peripheral region of a display substrate.

A dual-tub-isolated bi-directional protection device prevents carrier injection into the semiconductor substrate.

Segmented gate connection structures merge memory and peripheral region needs into one unified component, simplifying manufacturing process complexity.

Uses projecting regions as implantation masks to create vertical diodes, suppressing parasitic bipolar effects and eliminating alignment requirements.

Slot-die coating with high solute-fraction solutions eliminates solvent evaporation non-uniformity while maintaining manufacturing scalability.

An inner core strut supports a 2D material outer sleeve layer, enabling high-performance scalability while reducing manufacturing complexity.

A control device selects switching or linear modes to discharge inverter capacitors using existing semiconductor switches.

Buffer amplifier maintains voltage levels to resolve input signal degradation while reducing impedance in high sensitivity sense circuits.

A deep p+ layer extends the depletion region into the drift area, reducing electric field concentration at the gate oxide film.

A delta monolayer of dopant sits between an epitaxy doped semiconductor layer and a metal semiconductor alloy contact to lower interface resistance.

Laser processing forms precise openings in resin films to position gate electrodes, eliminating complex peeling steps required by rigid glass substrates.

A semiconductor memory device uses dummy active area patterns to distribute storage node contacts across the periphery region.

A semiconductor structure differentiates source-drain to gate distances across core and IO regions using epitaxial SiGe strained layers.

A semiconductor device fabrication method forms a silicon carbon oxynitride oxide layer on a silicon carbon nitride cap layer to create spacers adjacent to gate structures.

Directional etching creates vertical nanowires with alternate channel materials, reducing mask levels while maintaining high density.

A stacked solid-state imaging device uses microbumps to electrically connect photoelectric conversion substrates with memory circuits.

A programmable non-volatile memory cell stores data by modulating threshold voltage levels across multiple programming cycles.

A cascoded NMOS ESD protection circuit uses capacitive coupling to actively turn on transistors and shunt discharge currents.

Offset contact plugs prevent bridge formation and leakage current in high-density semiconductor devices.

Oblique epitaxial layers increase metal-semiconductor contact area, lowering parasitic resistance and boosting drive current.

Nickel carrier substrates enable high-temperature processing of amorphous IGZO transistors before transfer to bio-degradable polyvinyl alcohol films.

A bipolar junction transistor integrates a pickup region into its source finger to set substrate potential and shunt electrostatic discharge current.

A Z2-FET memory array uses shared transistor regions to handle high currents without enlarging the chip footprint.

A buried channel beneath the dual conversion gain switch provides an electrical path for excess charge overflow to the capacitor.

Optimizing hydrogen partial pressure during chemical vapor deposition increases sp2 bonding in amorphous carbon monolayers to restore electrical conductivity.

A guided mode resonance optical filter incorporates a reflector to reduce image sensor size and minimize optical crosstalk between adjacent pixels.

A low concentration impurity region in the channel area increases carrier density within the amplifying transistor.

A semiconductor device integrates a polysilicon resistor between thyristor regions to direct undesired current flow.

A pixel electrode structure integrates capacitor functions to expand display aperture area within compact switching element layouts.

Doped semiconductor substrate outer electrode eliminates polysilicon recess processes, reducing memory real estate usage by 30%.

Oxidized spacers isolate gate electrodes in stacked nanowire FETs to define a gate-all-around configuration.

A gate driver circuit measures collector-emitter voltage to dynamically adjust base current magnitude.

Redundant lower and upper layer data lines minimize parasitic capacitance between gate and data lines, eliminating flicker and streaky luminance unevenness.

Hydrogen inactivates magnesium in a co-doped GaN layer to form precise n-type regions, resolving ion implantation damage and improving breakdown voltage.

Conductive layers form a capacitive force sensor within the display panel to measure touch pressure without increasing device complexity.