Planar Double Gate Semiconductor Device with High-K Dielectric
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Solution Overview
Problem
Conventional semiconductor devices with thick buried oxide for back gates result in less control and higher power consumption due to increased back-gate voltage, which is not efficiently managed in dual-gate semiconductor devices.
Innovation Solution
A semiconductor device and fabrication method utilizing a graphene layer to form a thicker channel with a thinner back-gate dielectric layer, allowing for reduced bias voltage and lower power consumption, and implementing high-k/metal gate technology for both front and back gate regions with separate lightly doped regions and silicide layers for improved control and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thick buried oxide layer is used for back gate, then the device structure is simpler and manufacturing is easier, but the back-gate control is reduced and power consumption increases
Solution Approach 1:
The patent changes the dielectric parameter by using high-k material instead of conventional silicon dioxide for the back-gate dielectric layer. This high-k material provides higher capacitance per unit area, enabling effective back-gate control with lower voltage, thus reducing power consumption while maintaining manufacturing feasibility
Solution Approach 2:
The patent employs a composite structure combining high-k dielectric material with metal gate electrodes for both front and back gates. This composite approach enables independent control of front and back gates with improved electrostatic control and reduced power consumption compared to conventional single-material structures
2Device complexity
If a thick buried oxide layer is used for back gate, then the device structure is simpler, but the back-gate control is reduced
Solution Approach 1:
The patent changes the dielectric constant parameter by using high-k material, which provides higher capacitance and improved electrostatic control for the back gate. This enhances the reliability of back-gate control without significantly increasing device complexity, as the high-k layer is integrated into the existing MOSFET structure
Solution Approach 2:
The composite structure of high-k dielectric with metal gate electrodes provides superior electrostatic control for both front and back gates. This composite approach enables independent gate control with enhanced reliability while maintaining reasonable device complexity through systematic integration
3Device complexity
If conventional bulk technology is used, then the device structure is simpler, but the electrostatic characteristics are inferior and leakage currents are higher
Solution Approach 1:
The patent transitions from conventional bulk technology to a planar FD-SOI structure with thin silicon film, effectively moving to a different dimensional regime. This thin-film approach provides superior electrostatic control over the channel while managing complexity through planar fabrication processes
Solution Approach 2:
The patent employs a composite structure combining thin silicon channel with high-k dielectric and metal gate materials. This composite approach delivers enhanced electrostatic characteristics and reduced leakage currents compared to bulk technology, while maintaining compatibility with planar fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a dual-gate semiconductor device with reduced power consumption and enhanced control over the back gate, enabling more efficient operation and lower power usage while maintaining the same level of controllability as the front gate, suitable for CMOS logic and other applications.
Implementation Method 1
a first dielectric layer disposed adjacent to a first side of the channel... a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers
Implementation Method 2
a first silicide layer disposed above the third non-insulative region, and a second silicide layer disposed below the third non-insulative region
Implementation Method 3
a first non-insulative region disposed between the first dielectric layer and the substrate... a second non-insulative region disposed above the second dielectric layer... a third non-insulative region disposed adjacent to a third side of the channel
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.