OLED Display Oxide Polysilicon Transistor Integration
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Solution Overview
Problem
Organic light emitting diode (OLED) displays formed with only oxide thin film transistors are limited in overall capacity due to lower electron mobility compared to polycrystalline silicon-based transistors, necessitating a solution that combines the advantages of both oxide and polycrystalline silicon semiconductor layers for enhanced performance.
Innovation Solution
An OLED display structure and manufacturing method that incorporates a substrate with oxide and polycrystalline silicon semiconductor layers, utilizing etching stopper layers to connect electrodes and control etching processes, allowing for stable integration of oxide and polycrystalline silicon thin film transistors with a simple structure, thereby improving uniformity and electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If only oxide thin film transistors are used in OLED display, then uniformity is improved, but electron mobility is limited
Solution Approach 1:
The invention divides the transistor structure into two distinct semiconductor layers: an oxide semiconductor layer (first semiconductor layer) and a polycrystalline silicon semiconductor layer (second semiconductor layer). Each layer serves specific functions - the oxide layer provides uniformity and the polycrystalline silicon layer provides high electron mobility, thus resolving the contradiction by segmenting the semiconductor functionality.
Solution Approach 2:
The invention uses a composite semiconductor structure combining oxide semiconductor and polycrystalline silicon materials. This composite approach allows the device to simultaneously achieve the uniformity characteristics of oxide semiconductors and the high electron mobility of polycrystalline silicon, directly resolving the technical contradiction.
2Speed
If only polycrystalline silicon-based thin film transistors are used, then electron mobility is improved, but uniformity deteriorates
Solution Approach 1:
The transistor is segmented into two semiconductor layers with distinct material properties. The oxide semiconductor layer (first layer) provides the uniformity that polycrystalline silicon lacks, while the polycrystalline silicon layer (second layer) provides the electron mobility that oxide semiconductor lacks.
Solution Approach 2:
By combining oxide semiconductor and polycrystalline silicon in a layered composite structure, the invention achieves both high electron mobility from the polycrystalline silicon and high uniformity from the oxide semiconductor, resolving the contradiction between these two properties.
3Speed
If complex structure is used to integrate oxide and polycrystalline silicon transistors, then performance is improved, but device complexity increases
Solution Approach 1:
The invention merges the oxide semiconductor layer and polycrystalline silicon layer into a single integrated transistor structure that shares common components such as the gate electrode, source electrode, and drain electrode. This merging approach achieves high performance through material combination while avoiding the need for separate transistor structures, thus reducing overall device complexity.
Solution Approach 2:
The dual-layer semiconductor structure serves multiple functions simultaneously: the oxide layer provides uniformity and interface quality, the polycrystalline silicon layer provides high electron mobility, and together they form a complete transistor structure that can be controlled by a single gate electrode, reducing the need for additional control components.
Data Source
AI summary
An OLED display including a substrate main body; a first gate electrode and a second semiconductor layer; a gate insulating layer on the first gate electrode and the second semiconductor layer; a first semiconductor layer and a second gate electrode overlying the first gate electrode and the second semiconductor layer, respectively; etching stopper layers contacting portions of the first semiconductor layer; an interlayer insulating layer on the first semiconductor layer and the second gate electrode and including contact holes exposing the plurality of etching stopper layers, respectively; a first source electrode and a first drain electrode on the interlayer insulating layer and the contact holes being indirectly connected to the first semiconductor layer via the etching stopper layers or directly connected to the first semiconductor layer; and a second source electrode and a second drain electrode on the interlayer insulating layer being connected to the second semiconductor layer.