SiC Trench Gate Field Relief via Deep p+ Layer
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Solution Overview
Problem
Silicon carbide semiconductor devices with trench gate structures face high electric field concentrations at the gate oxide film, leading to potential breakdown, especially when subjected to high voltages, due to their increased electric-field breakdown strength compared to silicon semiconductor devices.
Innovation Solution
The implementation of a trench gate structure with a thicker bottom wall gate oxide film and a deep, high-concentration electrically conductive layer that extends beyond the trench depth, reducing electric field concentration by allowing the depletion layer to extend into the drift layer, thereby alleviating the stress on the gate oxide film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a trench gate structure is applied to increase channel density and electric current capacity, then the device can pass further increased electric current, but the gate insulation film is subjected to high electric field concentration (10 MV/cm at 1200V drain voltage) causing easy breakdown at corner areas
Solution Approach 1:
The patent applies local quality by forming a gate insulation film with non-uniform thickness, specifically making the film thicker at the bottom wall of the trench (200nm) compared to the sidewalls (40nm). This local variation in film thickness provides enhanced insulation strength precisely where the electric field concentration is highest (at the bottom wall corner areas), thereby preventing breakdown while maintaining the trench gate structure's current-carrying capability.
Solution Approach 2:
The patent changes the parameter of gate insulation film thickness from a uniform value to a variable value that depends on the location within the trench. By controlling the oxidation process to create different thicknesses at different locations (thicker at bottom, thinner at sidewalls), the patent optimizes the electric field distribution and prevents concentration-induced breakdown while maintaining device performance.
2Reliability
If the gate insulation film thickness is increased at the bottom wall to reduce electric field concentration, then the film thickness becomes five times greater than the sidewall (200nm vs 40nm), but this creates an asymmetric structure that complicates the manufacturing process
Solution Approach 1:
The patent utilizes the self-service principle by exploiting the natural crystallographic properties of the SiC substrate. The (000-1) c-plane substrate inherently provides different oxidation rates for different crystal planes: the c-plane bottom wall oxidizes five times faster than the a-plane sidewalls. This self-differentiating oxidation behavior automatically creates the desired non-uniform film thickness profile without requiring complex external control mechanisms or additional processing steps.
Solution Approach 2:
The patent employs thermal oxidation processes where the oxidation rate is dependent on the crystal plane orientation. The c-plane substrate exhibits anisotropic oxidation behavior during thermal processing, with the bottom wall (c-plane) oxidizing at a rate five times greater than the sidewalls (a-plane). This thermally-driven differential oxidation naturally produces the required asymmetric film thickness distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the electric field concentration at the gate oxide film, enhancing the device's ability to withstand high voltages without damaging the gate oxide film, thus improving the reliability and performance of silicon carbide semiconductor devices.
Implementation Method 1
When using such a c-plane substrate to prepare a gate oxide film in the trench, having the trench sidewall placed on the 'a' plane and the bottom wall placed on 'c' plane, by thermal oxidation, the 'c' plane has an oxidation rate five times greater than that of the 'a' place.
Implementation Method 2
a second electrically conductive type deep layer which is located in an area spaced from the trench with the base region being intervened, has a depth approximately equal to or greater than that of the trench and has a concentration approximately equal to or greater than that of the base region
Data Source
AI summary
An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n−-type drift layer to extend into the n−-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.