Z2-FET Memory Array With Shared Transistor Regions
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) comprising Z2-FET type memory cells faces challenges in reducing size while ensuring selection transistors can withstand high currents during low-impedance states.
Innovation Solution
The memory array design incorporates Z2-FET type memory cells with MOS-type selection transistors, where memory cells in the same column share a common front gate connected to a word line, and selection transistors have a larger gate width to handle higher currents without increasing the chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selection transistors are designed to withstand high currents (300 μA to 1 mA), then reliability is improved, but device area increases
Solution Approach 1:
Multiple selection transistors share a common drain region and common source region, merging their terminal structures. This allows the transistors to handle high currents collectively while reducing the total area required compared to completely separate transistor structures.
Solution Approach 2:
The common drain region and common source region serve multiple selection transistors simultaneously, making these regions multi-functional. This universal structure enables high current handling capability across multiple transistors without proportionally increasing the memory array footprint.
2Reliability
If selection transistors have larger gate width to handle higher currents, then current handling capability is improved, but device complexity increases
Solution Approach 1:
The selection transistors share common drain and source regions, merging their terminal structures. This reduces the overall number of discrete regions required while maintaining large effective gate widths for high current handling, thereby reducing structural complexity.
Solution Approach 2:
The gate regions maintain larger widths locally to ensure high current handling capability, while the drain and source regions are shared universally across multiple transistors. This local differentiation optimizes current handling where needed while reducing overall complexity through sharing.
Data Source
AI summary
A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.