Semiconductor Structure with Asymmetric Gate Distances
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Solution Overview
Problem
The existing semiconductor manufacturing techniques fail to effectively adjust the distance between source/drain regions and gates for core and IO circuits, leading to performance deviations in IO transistors due to shared manufacturing processes.
Innovation Solution
A semiconductor structure and manufacturing method that differentiate the distance between source/drain regions and gates for core and IO circuits by forming recesses in the substrate and depositing an epitaxial SiGe layer, with the second distance being at least 1.5 times the first distance, allowing for tailored performance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the same manufacturing process is used for both core circuit transistors and IO circuit transistors, then manufacturing efficiency is improved, but the performance precision of IO circuit transistors deteriorates
Solution Approach 1:
The patent applies local quality by forming different distance structures for different circuit regions within the same substrate. Specifically, first distance structures are formed in the core circuit region while second distance structures are formed in the IO circuit region, allowing each region to have optimized transistor characteristics suited to its specific performance requirements while using a unified manufacturing process
2Speed
If the distance between source/drain regions and gates is optimized for core circuit transistors, then the operating speed of core circuit is improved, but the response speed of IO circuit transistors becomes too fast causing operational flaws
Solution Approach 1:
The patent implements local quality by creating region-specific distance structures that control transistor response speeds differently across the substrate. The first distance structures in the core circuit region enable fast operating speeds, while the second distance structures in the IO circuit region provide slower, more controlled response speeds that match external circuit requirements, preventing operational flaws
3Manufacturing precision
If different manufacturing processes are used for core circuit transistors and IO circuit transistors, then the performance requirements of both circuits are met, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct regions (core circuit region and IO circuit region) and forming different distance structures in each region. This allows performance optimization for both circuit types while maintaining a unified manufacturing process, avoiding the complexity of completely separate manufacturing processes
Solution Approach 2:
The patent uses parameter changes by varying the distance between source/drain regions and gates in different substrate regions. By controlling this geometric parameter differently in the core circuit region versus the IO circuit region, the patent achieves different transistor characteristics without changing the fundamental manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacturing of transistors that meet design requirements for both core and IO circuits, preventing abnormal operation by ensuring the correct response speed and performance alignment.
Implementation Method 1
an epitaxial layer is in the recess. the material of the epitaxial layer is SiGe
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first gate structures, a plurality of second gate structures, a first strained region, and a second strained region. The substrate has a first region and a second region. The first gate structures are disposed in the first region on the substrate. The second gate structures are disposed in the second region on the substrate. The first strained region is formed in the substrate and has a first distance from an adjacent first gate structure. The second strained region is formed in the substrate and has a second distance from an adjacent second gate structure, wherein the second distance is greater than the first distance.