TFT Substrate Redundant Data Line Parasitic Capacitance

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Solution Overview

Problem

Display defects such as flicker and streaky luminance unevenness occur in liquid crystal and organic electroluminescent display devices due to parasitic capacitance between data lines and gate lines in top gate TFTs with oxide semiconductor layers and channel light-shielding films.

Innovation Solution

A thin-film transistor substrate design with a redundant data line structure, where lower and upper layer data lines are disposed in different layers, reducing parasitic capacitance by overlapping and connecting them without additional electrode layers, and using an inorganic insulating film to minimize capacitance while maintaining transmittance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a redundant data line structure with lower and upper layer data lines is added to top gate TFTs with oxide semiconductor layers, then display defects such as flicker and streaky luminance unevenness are eliminated, but parasitic capacitance between data lines and gate lines increases causing gate signal dullness

Engineering Contradiction:
Improvedisplay qualityVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies dimensionality change by transitioning from a single-layer data line structure to a multi-layer structure where lower and upper layer data lines are disposed at different vertical positions. This spatial arrangement in multiple dimensions allows the data lines to overlap the semiconductor layer more effectively, reducing parasitic capacitance with gate lines while maintaining redundant structure benefits for display quality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the data line into two separate components: a lower layer data line and an upper layer data line. These segmented components are disposed at different vertical levels and connected through contact holes, allowing each segment to be optimized for reducing parasitic capacitance while maintaining the overall redundant structure that eliminates display defects

Inventive Principle:
Principle #1Segmentation

2Reliability

If additional electrode layers are added to create redundant data lines, then display defects are reduced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvedisplay qualityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent achieves multi-functionality by designing the lower layer data line to serve dual purposes: it acts as a data transmission line and simultaneously functions as a light-shielding film. This eliminates the need for separate light-shielding layers, reducing overall device complexity while maintaining the redundant data line structure benefits

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the light-shielding function with the lower layer data line structure, combining two functional elements into one. This integration reduces the number of separate layers and components needed, simplifying the overall device structure while achieving both display defect reduction and parasitic capacitance minimization

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10971527B2Thin-film transistor substrate including data line with lower layer data line and upper layer data line, and liquid crystal display device and organic electroluminescent display device including same
Publication Date: 2021.04.06 SHARP KK
  • US10971527B2 patent drawing
  • US10971527B2 patent drawing
  • US10971527B2 patent drawing

AI summary

The thin-film transistor substrate of the present invention includes a gate line; a data line; one or more thin-film transistors; and a stack disposed on the insulating substrate and sequentially including a first line layer, a second line layer, and a third line layer, at least one of the thin-film transistors being connected to the gate line and the data line, at least one of the thin-film transistors including a lower layer gate electrode disposed in the first line layer, and an upper layer gate electrode disposed in the second line layer, the gate line being disposed in the first line layer, the data line including a lower layer data line disposed in the second line layer and an upper layer data line disposed in the third line layer, the gate line intersecting at least one of the lower layer data line or the upper layer data line.