Gate Connection Structure for Semiconductor Memory Integration
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Solution Overview
Problem
The complexity of manufacturing processes for semiconductor memory devices increases due to differing structural designs of MOS transistors in memory cells and peripheral regions, making effective integration and simplification challenging.
Innovation Solution
A semiconductor memory device design that includes a gate connection structure electrically connected to the gate structure on the peripheral region, formed partly on the top surface of a gate capping layer, allowing concurrent formation with other connection structures for process integration and simplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different structural designs are used for MOS transistors in memory cells and peripheral regions to meet product specifications and density requirements, then device functionality and performance are improved, but manufacturing process complexity increases
Solution Approach 1:
The gate connection structure is divided into two distinct parts: a first part that penetrates the gate capping layer to contact the gate electrode, and a second part disposed on the top surface of the gate capping layer. This segmentation allows each part to be optimized for its specific function while being formed through a unified manufacturing process, thereby maintaining device functionality without increasing manufacturing complexity
Solution Approach 2:
The gate connection structure is designed to serve multiple functions: it provides electrical connection between the gate electrode and external circuits, establishes proper potential distribution, and enables concurrent formation with other connection structures in the same manufacturing step. This multi-functionality allows different structural designs in memory cells and peripheral regions to be manufactured using the same process, reducing manufacturing complexity while maintaining adaptability
2Manufacturing precision
If separate manufacturing processes are used for memory cell and peripheral region devices, then structural requirements are met, but process integration and simplification are hindered
Solution Approach 1:
The gate connection structure merges the connection needs of both memory cell and peripheral region devices into a single unified structure. The first part penetrating the gate capping layer and the second part on the top surface work together to provide electrical connection, allowing concurrent formation with other connection structures in the same manufacturing step, thereby achieving process integration while meeting structural requirements
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.