DRAM Capacitor Arrangement Orthohexagonal Layout
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Solution Overview
Problem
In semiconductor devices, the miniaturization of capacitors leads to decreased capacitor capacitance, increasing the number of refresh operations and power consumption in DRAM, as the capacitor diameter decreases with the minimum processing size, making it difficult to maintain sufficient electrical charge storage and reduce power consumption.
Innovation Solution
The arrangement of capacitors with centers displaced from the intersection of signal lines, forming an orthohexagon pattern, allows for an enlarged capacitor diameter while maintaining the same cell size, thereby increasing capacitor capacitance by adjusting the line pitches of word and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor diameter is reduced to achieve miniaturization, then device density increases, but capacitor capacitance decreases
Solution Approach 1:
The patent transitions from a conventional square grid arrangement to an orthohexagonal arrangement, utilizing a different geometric dimensioning system. This dimensional change in the layout pattern allows capacitors to be positioned more efficiently in the available space, increasing the effective packing density while maintaining larger individual capacitor dimensions, thereby preserving capacitance.
Solution Approach 2:
The patent introduces asymmetry by displacing capacitor centers from the signal line intersections and arranging them in an orthohexagonal pattern rather than a symmetric square grid. This asymmetric positioning optimizes the use of space around each capacitor, allowing for larger capacitor diameters while maintaining high device density through the irregular but structured orthohexagonal arrangement.
2Productivity
If capacitor diameter is reduced, then the number of cells per area increases, but the number of refresh operations increases
Solution Approach 1:
By adopting the orthohexagonal arrangement, the patent achieves higher cell packing density through a different geometric dimensioning approach. This allows more cells to be accommodated per unit area while maintaining sufficient capacitor size, thereby reducing the frequency of refresh operations needed to maintain data integrity.
Solution Approach 2:
The patent changes the geometric parameters of the layout from a standard square grid to an orthohexagonal pattern with specific angular relationships (60度和120度). This parameter change in the arrangement geometry enables optimized space utilization that maintains larger capacitor dimensions, reducing refresh operation requirements while increasing cell density.
3Length of moving object
If capacitor diameter is reduced, then device miniaturization is achieved, but power consumption increases
Solution Approach 1:
The orthohexagonal arrangement represents a dimensional change in the layout strategy that allows for more efficient space utilization. This enables device miniaturization through better packing while maintaining larger capacitor diameters, thereby reducing the number of refresh operations and lowering overall power consumption despite the smaller device footprint.
Solution Approach 2:
The asymmetric orthohexagonal positioning of capacitors, with centers displaced from signal line intersections, optimizes the spatial distribution of capacitive elements. This asymmetric arrangement maintains larger effective capacitor areas within the miniaturized device structure, reducing refresh frequency and power consumption while achieving compact device dimensions.
Data Source
AI summary
The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to b5; and multiple capacitors. Respective center positions 4 of the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.