Semiconductor Pillar Formation Using ARDE
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Solution Overview
Problem
Conventional methods for forming three-dimensional contacts in semiconductor devices, especially for DRAM devices with critical dimensions less than 20 nanometers, are complex and costly, and result in undesirable structural characteristics due to aspect ratio dependent etching, leading to increased contact resistance and performance issues.
Innovation Solution
A method involving a patterned masking material with parallel line structures and trenches at specific angles, followed by aspect ratio dependent etching, to form elongate semiconductive pillars with controlled lateral dimensions and shapes, reducing contact resistance and improving alignment margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional methods are used to form three-dimensional contacts, then contact surface area is increased, but contact resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from conventional planar contacts to three-dimensional contacts by forming contacts that extend vertically into the substrate. The method creates 3D contact structures with increased surface area by utilizing vertical depth rather than only lateral expansion, thereby reducing contact resistance through enhanced contact area without increasing lateral device dimensions.
Solution Approach 2:
The patent performs preliminary patterning of the substrate before contact formation to define contact regions. Mask structures are formed in advance to guide subsequent etching and contact material deposition, ensuring proper alignment and positioning of three-dimensional contacts before the actual contact formation process occurs.
2Area of stationary object
If conventional methods are used to form three-dimensional contacts, then contact surface area is increased, but device complexity and cost increase
Solution Approach 1:
The patent combines multiple process steps into integrated sequences. The mask formation, etching, and contact material deposition are merged into a coordinated process flow where single-layer masks perform multiple functions, and etching parameters are optimized to simultaneously achieve contact hole formation and lateral dimension control in one operation, reducing the total number of discrete process steps.
Solution Approach 2:
The patent utilizes aspect ratio dependent etching (ARDE) by controlling etch parameters such as gas flow rates, pressure, and temperature to achieve self-adjusting etch rates. By modifying etch chamber conditions, the process automatically compensates for varying aspect ratios, forming contacts with consistent lateral dimensions despite differences in contact depth, thereby simplifying process control.
3Area of stationary object
If aspect ratio dependent etching is used, then three-dimensional contacts are formed, but lateral dimension control deteriorates
Solution Approach 1:
The patent exploits aspect ratio dependent etching (ARDE) by carefully controlling etch parameters including gas composition, pressure, and temperature. By adjusting these parameters, the etch rate becomes dependent on the aspect ratio of the contact hole, allowing deeper contacts to be formed with slower etching that maintains lateral dimension control, while shallower regions etch faster. This parameter optimization enables simultaneous achievement of increased contact depth and controlled lateral dimensions.
Solution Approach 2:
The patent replaces mechanical alignment and physical mask dimension control with a chemically-driven self-adjusting etching process. Instead of relying on precise mask lateral dimensions to define contact size, the process uses chemical etching parameters to automatically regulate lateral etching based on the developing aspect ratio, substituting chemical feedback control for mechanical precision requirements.
4Productivity
If feature dimensions are reduced, then device density increases, but contact resistance increases
Solution Approach 1:
The patent compensates for reduced lateral contact dimensions by extending contacts vertically into the substrate. As device features are scaled down laterally to increase density, the contact structures transition to three-dimensional forms with increased vertical depth, maintaining or increasing total contact surface area despite smaller lateral footprints, thereby preserving low contact resistance in high-density devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation and alignment of contacts, reduces contact resistance, and enhances the performance and reliability of semiconductor devices by controlling the lateral dimensions and shapes of semiconductive pillars, thereby improving feature density and reducing the risk of shorts and junction leakage.
Implementation Method 1
Portions of the hard mask material not covered by the elongate pillar structures are subjected to aspect ratio dependent etching to form a patterned hard mask material comprising elongate hard mask structures
Data Source
AI summary
A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.