DRAM Trench Capacitor Structure on SOI Substrate
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Solution Overview
Problem
Current memory devices with trench capacitors face challenges in optimizing device density and capacitance while minimizing real estate usage and eliminating the need for complex polysilicon recess processes and Arsenic-doped Silicate Glass (ASG) diffusion processes.
Innovation Solution
The development of a memory device structure that includes trench capacitors with a doped semiconductor substrate outer electrode, a conductive fill material inner electrode, and a node dielectric layer, positioned centrally under a semiconductor device with a gate structure, source, and drain region, which eliminates the need for a strap region and allows for a single polysilicon fill process without polysilicon etching, enhancing device density and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench capacitors are used to meet scaling demands for high performance DRAM, then capacitance is improved, but device complexity increases due to the need for complex polysilicon recess processes and Arsenic-doped Silicate Glass diffusion processes
Solution Approach 1:
The patent extracts and eliminates the complex polysilicon recess process and ASG diffusion process from the manufacturing sequence by using a simplified trench capacitor structure that achieves sufficient capacitance without these additional steps, thereby reducing process complexity while maintaining reliability
Solution Approach 2:
The patent changes the doping parameters and trench dimensions to achieve sufficient capacitance with a simpler process. Specifically, it uses a dopant level of about 10^19 atoms/cm³ and optimizes the trench geometry to provide the required capacitance without requiring the complex polysilicon recess and ASG diffusion processes
2Ease of manufacture
If traditional trench capacitor designs are used, then manufacturing process is established, but real estate usage is increased reducing device density
Solution Approach 1:
The patent transitions from a planar capacitor design to a three-dimensional trench capacitor structure. By etching trenches into the substrate and forming capacitors vertically, it achieves higher capacitance density and reduces the horizontal real estate required per capacitor, thereby improving device density while maintaining ease of manufacture through established trench etching processes
Solution Approach 2:
The patent nests the trench capacitor structure within the semiconductor substrate, with the trench capacitor positioned centrally under the semiconductor device. This nested configuration allows the capacitor to occupy vertical space rather than horizontal space, reducing the overall real estate footprint of the memory device
3Productivity
If trench capacitors with doped semiconductor substrate outer electrode are used, then device density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary doping of the semiconductor substrate to create the outer electrode region before trench formation. This preliminary action ensures that the doped region is already in place and properly configured, reducing the precision requirements for subsequent trench etching and electrode formation steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a 30% to 40% reduction in memory device real estate usage compared to traditional designs, improves device density, and provides robust trench capacitors with enhanced capacitance without requiring complex polysilicon recess processes or ASG diffusion steps.
Implementation Method 1
a doped portion of the semiconductor substrate, an inner electrode provided by a conductive fill material
Implementation Method 2
a node dielectric layer located between the outer electrode and the inner electrode
Implementation Method 3
Trench capacitors have replaced the planar storage capacitor in order to meet the scaling demands for high performance DRAM
Data Source
AI summary
A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.