Semiconductor Device Cap Layer Oxidation and Spacer Formation
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Solution Overview
Problem
Current DRAM units with buried gate structures face limitations in fabrication capability, affecting performance and reliability, particularly due to challenges in forming effective oxide layers during the oxidation process.
Innovation Solution
A method involving the formation of a substrate with defined memory and logic regions, where a stack structure and gate structure are created, followed by an oxidation process to form a silicon carbon oxynitride oxide layer on a silicon carbon nitride cap layer, and subsequent cap layer formation and etching to create spacers adjacent to the gate structure, ensuring precise control and protection of underlying layers during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxidation process is used to form oxide layer on cap layer, then fabrication process is simple, but oxide layer quality is poor and underlying layers are damaged
Solution Approach 1:
The patent divides the cap layer into multiple segments: first cap layer (silicon carbon nitride), oxide layer (silicon carbon oxynitride), and second cap layer (silicon nitride). This segmentation allows each layer to serve specific functions - the first cap layer provides a good interface with the gate structure, the oxide layer protects during etching, and the second cap layer provides structural support.
Solution Approach 2:
The oxidation process is performed preliminarily on the first cap layer before forming the second cap layer. This preliminary oxidation creates a protective oxide layer that prevents damage to underlying layers during subsequent etching processes, solving the problem of poor oxide layer quality and layer damage.
2Productivity
If etching is performed directly on cap layer, then process is fast, but cap layer and underlying layers are damaged
Solution Approach 1:
The oxide layer acts as an intermediary between the etching process and the cap layers. It provides a protective barrier during etching of the stack structure, preventing direct contact between etchants and the cap layers, thus avoiding damage while maintaining etching efficiency.
Solution Approach 2:
The second cap layer is formed beforehand to provide cushioning protection during the etching process. This pre-formed protective layer absorbs the harsh conditions of etching, preventing damage to the underlying first cap layer and gate structure.
3Reliability
If single cap layer is used, then structure is simple, but protection during etching is insufficient
Solution Approach 1:
The cap layer structure is segmented into three distinct layers with different materials and functions. The first cap layer (silicon carbon nitride) interfaces with the gate structure, the oxide layer (silicon carbon oxynitride) provides etching protection, and the second cap layer (silicon nitride) provides structural support and additional protection.
Solution Approach 2:
The patent uses composite material structure combining silicon carbon nitride, silicon carbon oxynitride, and silicon nitride layers. Each material is selected for its specific properties - silicon carbon nitride for good interface characteristics, silicon carbon oxynitride for etching resistance, and silicon nitride for structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication process by forming reliable oxide layers and spacers, improving the structural integrity and reliability of DRAM devices by preventing damage to the cap layers during etching and enabling precise patterning for bit line and contact structures.
Implementation Method 1
performing an oxidation process to form an oxide layer on the first cap layer
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.