Semiconductor Channel Structure with Inner Core Strut
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current silicon-based transistors are reaching performance and scalability limits, and alternative semiconductor materials like Ge and III-V semiconductors face challenges in ultra-thin body performance scalability and high costs.
Innovation Solution
The use of 2D layered channel materials, such as transition metal dichalcogenides and topological insulators, in a 3D semiconductor device architecture with a composite structure featuring a vertically extending inner core strut and a wrapping outer sleeve layer, allowing for enhanced channel performance and reduced horizontal profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative semiconductor materials like Ge and III-V semiconductors are used, then performance scalability is improved, but cost increases and ultra-thin body performance scalability remains challenging
Solution Approach 1:
The patent employs a composite channel structure combining silicon-germanium (SiGe) sacrificial material with 2D material deposition. The SiGe layer (5-20 nm thick) serves as both a structural template and a means to achieve lattice matching, while the subsequent 2D material layer provides the desired electronic properties. This composite approach enables ultra-thin body structures with improved performance scalability without requiring entirely new material systems, thus reducing manufacturing complexity and cost.
Solution Approach 2:
The patent utilizes controlled variation of germanium concentration in SiGe layers (ranging from 5% to 30% Ge) to optimize lattice matching and strain effects. By adjusting the Ge concentration parameter, the structure achieves both mechanical compatibility with surrounding layers and enhanced carrier mobility, improving performance scalability while maintaining compatibility with existing silicon-based manufacturing processes.
2Ease of manufacture
If conventional silicon-based transistors are used, then manufacturing is easier and cost is lower, but performance and scalability reach fundamental limits
Solution Approach 1:
The patent transitions from conventional planar or bulk silicon structures to vertically stacked 3D architectures with ultra-thin 2D material channels. This dimensional change enables continued scaling by exploiting the vertical dimension while maintaining compatibility with existing silicon manufacturing. The multi-layer stack structure (substrate, buffer, SiGe, 2D material, capping layers) allows for improved electrostatic control and higher device density without sacrificing manufacturability.
3Productivity
If ultra-thin body structures are implemented, then device density and integration are improved, but performance scalability of alternative materials becomes challenging
Solution Approach 1:
The patent introduces SiGe as an intermediary sacrificial layer that facilitates the formation of ultra-thin 2D material channels. The SiGe layer serves multiple functions: it provides a sacrificial template for defining the channel region, induces strain to enhance carrier mobility in the 2D material, and enables lattice matching during deposition. This intermediary approach allows ultra-thin body structures to achieve both high device density and maintained performance scalability through the mediating role of SiGe.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved current control and scalability, potentially leading to high-performance, low-power devices with reduced spatial requirements and the ability to operate without source/drain doping, while leveraging the unique electrical properties of 2D materials for efficient carrier conduction.
Implementation Method 1
The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device
Implementation Method 2
leveraging the unique electrical properties of 2D materials for efficient carrier conduction
Data Source
AI summary
A semiconductor device having a composite structure is disclosed, which includes a channel structure having an inner core strut that extends substantially along a channel direction of the semiconductor device and an outer sleeve layer disposed on the inner core strut. The inner core strut mechanically supports the sleeve member across a channel length of the semiconductor device.