Display Clock Recovery Circuit With Dynamic Delay Voltage Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current clock data recovery circuits in displays are limited by their multi-stage delay chain using inverters, which restricts the operating frequency and bandwidth, making it difficult to recover data from high-speed clock data signals effectively.
Innovation Solution
A clock recovery circuit that includes a delay line with multiple stages and a mode generator, which selects between two different driving voltages to generate delayed clocks, allowing for the comparison of unit delay times with a preset reference delay time to adjust the operating frequency and achieve a wide bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-stage delay chain using inverters is used to recover the clock, then the clock recovery function is achieved, but the operating frequency range is limited and bandwidth is restricted
Solution Approach 1:
The delay units dynamically switch between two different driving voltages (first driving voltage and second driving voltage) based on a mode signal. This dynamic voltage switching allows the delay chain to adapt its delay characteristics to different frequency ranges, enabling both high-speed operation and wide bandwidth coverage without being limited to a fixed operating frequency range.
Solution Approach 2:
The invention changes the driving voltage parameter of the delay units between two distinct voltage levels. By switching the driving voltage, the delay time of each stage is adjusted, which enables the system to operate effectively across a wide bandwidth range while maintaining accurate clock recovery at different frequencies.
2Productivity
If the multi-stage delay chain is designed for high-speed operation, then high-frequency clock recovery is achieved, but the frequency range and adaptability are reduced
Solution Approach 1:
The system uses a mode generator to produce a mode signal that dynamically controls the driving voltage of delay units based on the detected frequency characteristics of the input clock data signal. This allows the system to automatically adapt between high-speed optimization and wide-range coverage, achieving both high productivity and broad adaptability.
Solution Approach 2:
The delay units are designed to perform multiple functions by switching between two driving voltages: one voltage level optimizes for high-speed operation while the other extends the frequency range. This multi-functionality allows a single delay chain structure to handle both high-frequency data recovery and wide bandwidth adaptation effectively.
Data Source
AI summary
A clock data recovery circuit of a display suitable for recovering a clock from a clock data signal. The clock data recovery circuit includes a clock recovery circuit configured to delay an input clock through delay units of multiple stages, and output delayed clocks from the delay units, respectively; and a data recovery circuit configured to recover data of a clock data signal using a recovered clock selected among the delayed clocks.