Display Substrate ESD Layout Using Inclined Series Transistors
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Solution Overview
Problem
Existing display substrate technologies face challenges in efficiently utilizing wiring space due to inefficient layouts of Electro-Static discharge (ESD) protection units, which can lead to increased risk of damage to traces and circuits and reduced product yield.
Innovation Solution
The display substrate incorporates ESD protection units with transistors connected in series, arranged along a first inclination direction forming a preset angle with the gate line direction, optimizing the use of wiring space and reducing the risk of ESD damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection units are disposed on the display substrate, then protection against ESD damage is improved, but wiring space is wasted and the risk of burning power supply lines increases
Solution Approach 1:
The patent changes the arrangement dimension of transistors in ESD protection units from parallel alignment with gate lines to inclined alignment at angles of 10°-70° relative to gate lines. This dimensional change in orientation reduces the projected area occupied by ESD protection units along the gate line direction, thereby minimizing wiring space occupation while maintaining ESD protection functionality.
Solution Approach 2:
The patent modifies the geometric parameter of transistor arrangement by specifying inclination angles between 10°-70° relative to gate line direction. This parameter optimization reduces the effective area occupied by ESD protection units, allowing better space utilization and reduced current density in power supply lines while preserving ESD protection capability.
2Ease of manufacture
If transistors are arranged parallel to gate line direction, then manufacturing is simplified, but wiring space occupation increases and current density increases
Solution Approach 1:
The patent transitions from zero-dimensional parallel alignment to angled alignment in a different spatial dimension, where transistors are arranged at inclination angles of 10°-70° relative to gate lines. This angular arrangement reduces the projected footprint along the gate line direction, minimizing wiring space occupation while remaining compatible with existing manufacturing processes.
Solution Approach 2:
The patent introduces asymmetric arrangement of transistors relative to gate lines by specifying inclination angles of 10°-70°. This asymmetric configuration optimizes space utilization by reducing the effective area occupied along the gate line direction, thereby decreasing wiring space requirements and current density while maintaining manufacturing feasibility.
3Device complexity
If ESD protection units use conventional layout, then design is simplified, but current density increases causing burning risk
Solution Approach 1:
The patent applies angular arrangement of transistors at 10°-70° inclination angles to distribute current paths more effectively across the substrate. This spatial redistribution reduces current density concentration in power supply lines, lowering burning risk while maintaining straightforward ESD protection unit design and integration.
Data Source
AI summary
A display substrate and a display apparatus are provided. The display substrate includes: a display area and a non-display area located around the display area, wherein the non-display area includes: at least one Electro-Static discharge (ESD) protection unit, each ESD protection unit includes: multiple transistors connected in series, a first electrode of each transistor is connected with a gate, and the multiple transistors are arranged along a first inclination direction, a first preset included angle is provided between the first inclination direction and a first direction, the first preset included angle ranges from 10° to 80°, and the first direction is an extending direction of a gate line in the display area.