Display Device Gate Line Layout for Reduced RC Delay
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Solution Overview
Problem
Display devices face challenges in reducing RC delay and increasing display area efficiency due to the layout of gate lines and voltage lines, which limits the available space for the display area and affects driving margin.
Innovation Solution
The proposed display device configuration includes unit pixels with specific arrangements of gate lines, voltage lines, and data lines, where vertical gate lines are strategically placed between unit pixels to reduce their number, allowing for additional space to be used for supply voltage lines and capacitors, thereby reducing RC delay and enhancing the driving margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate lines are placed on both sides of unit pixels, then the display area is maximized, but the number of gate lines increases leading to increased RC delay
Solution Approach 1:
The patent extracts and removes gate lines from one side of the unit pixels, specifically eliminating the gate line on the second side while maintaining the gate line on the first side. This reduction in gate line quantity directly decreases the RC delay of the display device while preserving sufficient display area.
2Reliability
If more voltage lines and capacitors are added to reduce RC delay, then the driving margin improves, but the available space for display area decreases
Solution Approach 1:
The patent merges the functions of multiple gate lines by eliminating redundant gate lines on the second side of unit pixels. This consolidation reduces the total number of gate lines while maintaining the necessary electrical connections, thereby reducing RC delay without requiring additional voltage lines or capacitors that would consume display area.
Solution Approach 2:
The patent optimizes the spatial arrangement of remaining gate lines by positioning them strategically on the first side of unit pixels, utilizing the vertical dimension and spacing to maintain electrical connectivity while reducing horizontal space consumption. This dimensional optimization allows for reduced RC delay without sacrificing display area.
3Area of stationary object
If the number of gate lines is reduced to increase display area, then the display area increases, but the RC delay increases due to longer line lengths
Solution Approach 1:
The patent segments the gate line configuration into two distinct groups: gate lines on the first side of unit pixels (which are retained) and gate lines on the second side (which are removed). This segmentation allows for selective optimization, keeping necessary gate lines while eliminating redundant ones, thereby increasing display area while controlling RC delay through strategic placement.
Data Source
AI summary
A display device includes first and second unit pixels adjacent to each other in a first direction, and each including first to third pixels, a first voltage line on a first side of each of the first and second unit pixels, and extended in a second direction crossing the first direction, a data line on a second side of each of the first and second unit pixels, and extended in the second direction, first gate lines between the first side of the first unit pixel and the second side of the second unit pixel to not be on the second side of the first unit pixel and to not be on the first side of the second unit pixel, and extended in the second direction, and a second gate line connected to at least one of the first gate lines, and extended in the first direction.