Display Apparatus With Overlapping Gate Clock Phases
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Solution Overview
Problem
Flat panel display (FPD) devices with reduced data driver chips result in increased gate lines, leading to larger bezel widths and decreased pixel charging duration, which affects display performance.
Innovation Solution
A display apparatus with a printed circuit board (PCB) that includes a power management integrated circuit (PMIC) generating multiple gate clock signals and inversion gate clock signals with overlapping phases, applied to gate lines through a gate driver, which extends the duration of gate signals for pixel charging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of data driver chips is decreased, then manufacturing cost is reduced, but the number of gate lines increases causing larger bezel width
Solution Approach 1:
The gate clock signal transmission is segmented into multiple channels (first gate clock signal through fourth gate clock signal) transmitted through separate lines. This segmentation allows for more efficient signal distribution across the increased number of gate lines, enabling cost reduction through fewer data driver chips while managing the increased gate line complexity through structured signal division.
Solution Approach 2:
The patent utilizes both surfaces of the PCB for signal transmission - the first surface carries gate clock signals while the second surface carries inverted gate clock signals. This dimensional utilization of the PCB structure allows efficient routing of increased gate lines without proportionally increasing bezel width, as signals are distributed across multiple layers/dimensions of the circuit board.
2Ease of manufacture
If the number of data driver chips is decreased, then manufacturing cost is reduced, but pixel charging duration decreases
Solution Approach 1:
The patent generates multiple gate clock signals in advance with different phases (first through fourth gate clock signals) and their corresponding inverted versions. These pre-generated signals are distributed through dedicated lines to coordinate the charging operation across multiple gate lines simultaneously, ensuring adequate charging duration is maintained even with fewer data driver chips.
Solution Approach 2:
The overlapping phases of the gate clock signals ensure continuous and coordinated charging action across the display panel. By having multiple gate clock signals with overlapping active periods transmitted through separate lines, the system maintains continuous useful charging action across all pixels, preventing duration reduction despite using fewer data driver chips.
3Duration of action of moving object
If multiple gate clock signals with overlapping phases are generated, then pixel charging duration is enhanced, but PCB complexity increases
Solution Approach 1:
The patent combines the transmission of gate clock signals and inverted gate clock signals on both surfaces of the PCB in a structured manner. By merging the signal distribution function across both PCB surfaces and utilizing the insulation layer as a natural separator, the complexity of handling multiple signals is managed through integrated dual-surface routing rather than requiring separate complex routing for each signal type.
Solution Approach 2:
The PCB structure serves multiple functions simultaneously: the first surface transmits gate clock signals, the second surface transmits inverted gate clock signals, and the insulation layer provides both electrical isolation and structural support. This multi-functionality reduces overall system complexity by having the PCB perform multiple roles rather than requiring separate components for each function.
Data Source
AI summary
A display apparatus includes a printed circuit board (PCB). A power management integrated circuit (PMIC) is mounted on the PCB and is configured to generate first to fourth gate clock signals and first to fourth inversion gate clock signals. A phase of the first gate clock signal partially overlaps a phase of the second to fourth gate clock signal. Each of the first to fourth inversion gate clock signals has a phase opposite to that of a respective one of the first to fourth gate clock signals. A gate driver generates a plurality of gate signals based on the first to fourth gate clock signals and the first to fourth inversion gate clock signals and applies the plurality of gate signals to a plurality of gate lines. A display panel is connected to the plurality of gate lines.