Display Panel Gate Insulator Layout to Prevent Channel Shortening

The gate insulating layer is segmented into different regions with different thicknesses: a first region under the gate with greater thickness and a second region in the source and drain areas with smaller thickness. This segmentation allows selective plasma treatment - the thinner second region enables plasma gas to reach and reduce resistance in source/drain regions, while the thicker first region acts as a barrier preventing plasma gas from diffusing into the channel region, thus resolving the contradiction between improving conductivity and maintaining channel length precision

Different regions of the gate insulating layer are given different local properties (thickness values) to serve different functions. The region under the gate has greater thickness for protection, while the region in source/drain areas has smaller thickness for conductivity enhancement. This local differentiation allows the system to simultaneously achieve both improved source/drain conductivity and preserved channel length

The gate insulating layer is divided into functional segments with different thickness characteristics. The first region under the gate maintains adequate thickness even when aligned with the gate, while the second region in source/drain areas is intentionally made thinner. This segmentation allows the self-alignment method to achieve precise positioning while the thickness variation prevents harmful plasma diffusion, thus maintaining both alignment precision and threshold voltage stability

Instead of relying solely on the planar dimension (line width alignment) to control plasma diffusion, the invention introduces a vertical dimension (thickness variation) as the primary control mechanism. The gate insulating layer's thickness varies through the vertical dimension - thinner where plasma exposure is desired and thicker where protection is needed - thereby solving the channel length shortening issue without compromising alignment precision