Display Panel Compensation Semiconductor Layer Layout
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Solution Overview
Problem
Current display panels face challenges in achieving high-quality and high-resolution images due to limitations in pixel circuit design and transistor configurations, which affect the display's ability to efficiently transfer signals and maintain image quality.
Innovation Solution
The display panel incorporates a substrate with specific configurations of thin film transistors, including driving, compensation, switching, and emission control transistors, along with optimized gate and scan lines, and insulating layers to enhance signal transfer and reduce parasitic capacitance, allowing for improved image quality and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the scan line is positioned closer to the driving semiconductor layer, then the signal transfer distance is reduced, but the parasitic capacitance increases and crosstalk occurs
Solution Approach 1:
The patent repositions the compensation semiconductor layer in the planar dimension (closer to the driving semiconductor layer) while using the gate connection line to bridge the vertical gap to the scan line. This dimensional rearrangement optimizes the spatial layout to reduce parasitic capacitance between the compensation transistor and scan line, while maintaining efficient signal transfer through the gate connection line pathway.
Solution Approach 2:
The gate connection line acts as an intermediary element that electrically connects the scan line to the compensation gate electrode. This intermediary structure allows the scan line to be positioned optimally while still providing the necessary electrical connection to the compensation transistor, thereby reducing parasitic capacitance and crosstalk while maintaining signal transfer efficiency.
2Reliability
If the pixel circuit components are arranged to reduce parasitic capacitance, then image quality improves, but the device complexity increases
Solution Approach 1:
The gate connection line is merged with the scan line structure, where the gate connection line extends from the scan line to connect to the compensation gate electrode. This merging approach integrates multiple functions into a single structural element, reducing device complexity while achieving the goal of reduced parasitic capacitance and improved image quality.
Solution Approach 2:
The gate connection line serves multiple functions: it acts as part of the scan line structure, provides electrical connection to the compensation gate electrode, and optimizes the spatial arrangement to reduce parasitic capacitance. This multi-functionality reduces the need for separate dedicated connection structures, thereby simplifying the overall device complexity while improving image quality.
3Loss of time
If the compensation transistor is positioned closer to the driving transistor, then the RC delay is reduced, but the layout space requirements change
Solution Approach 1:
The gate connection line is configured to extend in a curved or angled path (first direction crossing the second direction) from the scan line to the compensation gate electrode. This curved routing optimizes the spatial utilization within the pixel circuit, allowing the compensation transistor to be positioned closer to the driving transistor to reduce RC delay, while efficiently using the available layout area.
Data Source
AI summary
The present disclosure provides a display panel. In order to reduce a parasitic capacitance that may occur between a data line and a semiconductor layer and a crosstalk caused by the parasitic capacitance, a display panel includes a substrate, a driving thin film transistor on the substrate, including a driving semiconductor layer and a driving gate electrode, a compensation thin film transistor on the substrate, including a compensation semiconductor layer and a compensation gate electrode, a node connection line electrically connecting the driving thin film transistor to the compensation thin film transistor, a scan line extending in a first direction on the substrate, and a gate connection line electrically connected to the scan line, which includes the compensation gate electrode, wherein the compensation semiconductor layer is closer to the driving semiconductor layer than the scan line when viewed on a plane.