Display Panel Semiconductor Layout for Horizontal Crosstalk Reduction
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Solution Overview
Problem
Thin film transistor liquid crystal display devices suffer from horizontal crosstalk due to capacitive coupling between data lines and common electrodes, resulting in decreased pixel brightness and uneven parasitic capacitance during positive and negative frame driving.
Innovation Solution
A display panel design where a second semiconductor layer is strategically positioned between the first and third metal layers to offset parasitic capacitance, ensuring equal capacitance values during both positive and negative frame driving, thereby mitigating capacitive coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a parasitic capacitance structure between data lines and common electrodes is formed using a semiconductor layer and an insulating layer, then the display device can be manufactured with standard processes, but horizontal crosstalk occurs due to unequal parasitic capacitance during positive and negative frame driving
Solution Approach 1:
The patent introduces a second semiconductor layer that is asymmetrically positioned relative to the first semiconductor layer. The first semiconductor layer is disposed between the common electrode and the data line, while the second semiconductor layer is disposed between the common electrode and the insulating layer. This asymmetric arrangement creates equal but opposite parasitic capacitances that cancel each other during positive and negative frame driving, eliminating horizontal crosstalk while maintaining compatibility with standard manufacturing processes
Solution Approach 2:
The patent modifies the electrical parameters of the parasitic capacitance structure by introducing a second semiconductor layer with specific positioning. By changing the spatial arrangement and electrical characteristics of the semiconductor layers, the parasitic capacitance values during positive and negative frame driving are equalized, transforming the system from having unequal capacitances (causing crosstalk) to equal capacitances (canceling crosstalk effects)
2Object-affected harmful factors
If the parasitic capacitance between data lines and common electrodes is reduced, then horizontal crosstalk is minimized, but the coupling effect of storage capacitors is weakened
Solution Approach 1:
The patent segments the parasitic capacitance into two distinct components: one formed by the first semiconductor layer between the common electrode and data line, and another formed by the second semiconductor layer between the common electrode and insulating layer. By separating the parasitic capacitance into these two segments, each contributing equally but oppositely, the net crosstalk effect is eliminated while the individual storage capacitor functions remain intact for maintaining pixel brightness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces horizontal crosstalk by equalizing parasitic capacitance, maintaining consistent pixel brightness and minimizing capacitive coupling issues between data lines and common electrodes.
Implementation Method 1
parasitic capacitance between the data line and the common electrode
Data Source
AI summary
A display panel includes a first substrate and a second substrate disposed opposite to each other and spaced apart from each other, and a second semiconductor layer. The first substrate includes a first base substrate, a first metal layer, a first semiconductor layer, and a second metal layer. The first metal layer is disposed on the first base substrate. The first semiconductor layer is disposed on the first metal layer. The second metal layer is disposed on the first semiconductor layer. The second substrate includes a second base substrate and a third metal layer. The third metal layer is disposed on the second base substrate. The second semiconductor layer is disposed between the first metal layer and the third metal layer. The first semiconductor layer is insulated from the second semiconductor layer.