Display Panel Gate Line Layout Around Hole Areas for Uniformity
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Solution Overview
Problem
Display non-uniformity in display panels due to differences in wiring loading between the winding line region and the display region, caused by the presence of a hole region for functional components, leading to uneven gate potentials of drive transistors.
Innovation Solution
The display panel design includes independent signal transmission lines in the winding line region, with cascaded gate drive units providing scan signals to adjacent rows of pixel circuits, and multiple layers of winding lines to distribute wiring uniformly across regions, reducing differences in loading and improving display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hole region is introduced to arrange functional components, then the device integration is improved, but display uniformity deteriorates due to wiring loading differences
Solution Approach 1:
The patent segments the signal transmission lines into multiple independent portions, with each portion passing through the winding line region separately. This segmentation allows independent optimization of each line's routing, balancing the wiring loading across different regions and reducing display non-uniformity while maintaining the hole region for functional components.
Solution Approach 2:
The patent applies local quality by making the wiring structure in the winding line region differ from the display region. Specifically, signal transmission lines are designed to pass through the winding line region independently, with adjusted routing and loading characteristics tailored to this specific area, thereby compensating for the display non-uniformity caused by the hole region.
2Length of stationary object
If signal transmission lines pass through the winding line region, then the border width is reduced, but wiring loading imbalance increases causing display non-uniformity
Solution Approach 1:
The signal transmission lines are divided into multiple segments, with each segment independently routed through the winding line region. This segmentation enables precise control over the loading of each line, allowing the border to be narrowed while maintaining display uniformity through balanced wiring distribution.
Solution Approach 2:
The patent utilizes multiple layers to route signal transmission lines through the winding line region. By distributing lines across different layers, the wiring loading is balanced in three-dimensional space, enabling border narrowing without compromising display uniformity.
3Manufacturing precision
If multiple layers of winding lines are used to distribute wiring uniformly, then display uniformity is improved, but device complexity increases
Solution Approach 1:
The patent employs multiple layers to route signal transmission lines, distributing the wiring load across vertical dimensions. This multi-layer approach achieves uniform wiring distribution and improved display uniformity while consolidating the wiring structure in a compact three-dimensional arrangement, rather than expanding horizontally.
Solution Approach 2:
The multiple layers are designed to serve multiple functions: they transmit scan signals, balance wiring loading, and enable border narrowing simultaneously. This multi-functionality reduces the need for separate structures, thereby limiting the increase in overall device complexity despite the multi-layer wiring configuration.
Data Source
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AI summary
A display panel, comprising a hole area (22), a winding area (24), a display area (21), and a non-display area (23). The winding area (24) is arranged around the hole area (22), and the display area (21) is arranged around at least part of the winding area (24). The display panel further comprises a first gate driving circuit (231), wherein the first gate driving circuit (231) is located in the non-display area (23) on one side of the display area (21). The first gate driving circuit (231) comprises a plurality of cascaded first gate driving units (2311), wherein each first gate driving unit (2311) provides a first scan signal to two adjacent rows of pixel circuits (210) by means of two first signal transmission lines (211), the first scan signal is capable of affecting gate potentials of driving transistors (T3) in the pixel circuits (210), the first signal transmission lines (211) are partially located in the winding area (24), and the parts of the first signal transmission lines (211) located in the winding area (24) are independent of each other.