Display Panel Shift Register Layout for Selective Row Refresh
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Solution Overview
Problem
Existing display panels consume high power due to the need to refresh all pixel rows simultaneously, preventing selective refresh or hold of arbitrary pixel rows, which affects power consumption and display requirements.
Innovation Solution
A display panel design with independent stage transfer and scan clock signals in shift register units, allowing for high or low-frequency refresh of any row without affecting sequential driving, achieved by connecting stage transfer output and scan output circuits to separate clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all shift register units output effective pulses of scan signals to refresh all pixel rows, then the display panel achieves complete pixel refresh, but power consumption increases
Solution Approach 1:
The patent divides the shift register units into different groups (first group and second group) that can be independently controlled. The first group outputs scan signals at a first frequency while the second group outputs at a second frequency, allowing selective refresh of different pixel row sets. This segmentation enables the display panel to refresh only necessary pixel rows at high frequency while reducing or stopping refresh of other rows, thereby resolving the contradiction between complete pixel refresh and power consumption.
2Adaptability or versatility
If shift register units operate independently with separate clock signals, then selective refresh of arbitrary pixel rows is enabled, but device complexity increases
Solution Approach 1:
The patent introduces a frequency control signal that can dynamically adjust the operating frequency of different shift register unit groups. This multi-functional control mechanism allows the same hardware structure to operate in different modes (all rows at same frequency, some rows at high frequency while others at low or zero frequency), achieving selective refresh capability without proportionally increasing device complexity.
3Use of energy by moving object
If scan signals are held at invalid level for some pixel rows, then power consumption is reduced, but sequential driving of shift register units must be maintained
Solution Approach 1:
The patent employs dynamic frequency control where the operating frequency of different shift register unit groups can be adjusted in real-time based on display requirements. During video display, some groups operate at high frequency while others are held at low or zero frequency. This dynamic control maintains the sequential driving capability of the shift register units while allowing selective reduction of scan signal output, thereby reducing power consumption without compromising the fundamental sequential operation reliability.
Data Source
AI summary
A display panel includes a shift register, multiple stage transfer clock lines and scan clock lines. The shift register includes multiple cascaded shift register units each including an input circuit, a stage transfer output circuit and a scan output circuit. The input circuit is electrically connected to an input terminal and a first node. The stage transfer output circuit is electrically connected to the first node, a stage transfer clock terminal, and a stage transfer output terminal. The stage transfer output terminal of the i-th stage shift register unit is electrically connected to the input terminal of the j-th stage shift register unit. The scan output circuit is electrically connected to the first node, a scan clock terminal, and a scan output terminal. The stage transfer clock terminal is electrically connected to the stage transfer clock line, and the scan clock terminal is electrically connected to the scan clock line.