Display Panel Trace Routing in Display Area
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Solution Overview
Problem
The existing display panel designs are limited in reducing the non-display area (frame) due to the presence of peripheral circuit traces, which restrict further minimization of the frame width.
Innovation Solution
The display panel incorporates a new routing method where traces are disposed within the display area, with scan lines and traces arranged perpendicularly to each other, and connected through via holes, allowing for reduced frame area occupation by eliminating the need for the non-display area traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If peripheral circuit traces are routed through the non-display area (frame), then the display module can connect thin film transistors to outer lead terminals, but the frame area cannot be further reduced
Solution Approach 1:
The patent applies dimensionality change by moving the trace routing from the planar non-display area into the display area, utilizing the vertical stacking of metal layers (first metal layer, second metal layer, third metal layer) to create three-dimensional trace paths. This allows traces to connect scan lines to driving chips while occupying display area rather than frame area, thereby reducing frame size.
Solution Approach 2:
The patent implements nesting by placing multiple trace layers (first traces in second metal layer, second traces in third metal layer) within the display area, with traces from different layers nested vertically above each other. This nested arrangement allows dense routing of peripheral circuit traces within the display area without interfering with the visual display function.
2Area of stationary object
If traces are disposed in the display area, then the frame area is reduced, but the routing complexity increases with multiple metal layers and via holes
Solution Approach 1:
The patent applies segmentation by dividing the trace routing function across multiple metal layers (second metal layer for first traces, third metal layer for second traces) and using via holes to connect between layers. This segmentation allows the routing to be broken into manageable segments that can be independently optimized, reducing the overall complexity compared to attempting to route all traces in a single layer.
Solution Approach 2:
The patent resolves routing complexity by transitioning from two-dimensional planar routing in the non-display area to three-dimensional routing utilizing multiple metal layers stacked vertically. This adds a vertical dimension to the routing architecture, allowing traces to pass through via holes between layers and reducing the need for complex lateral routing paths.
3Area of moving object
If scan lines and traces are arranged perpendicularly and connected through via holes, then space utilization is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes space utilization by arranging scan lines in a first direction in the first metal layer and traces in a second direction perpendicular to the first direction in the second and third metal layers, creating a perpendicular three-dimensional arrangement. This orthogonal stacking maximizes space utilization while the via holes provide precise vertical alignment between layers, reducing the manufacturing precision burden compared to lateral alignment.
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes: a substrate, including a display area; a first metal layer, including a plurality of scan lines; a second metal layer, including a plurality of first traces, wherein projections of the plurality of first traces on the substrate are located in the display area; and a driving chip, wherein at least a portion of the scan lines are connected to the driver chip through the first traces.