Display Driving Circuitry for Leakage-Free Reset Isolation
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Solution Overview
Problem
In existing driving circuitry, negative drift in the threshold voltage of transistors leads to incomplete cutoff of the resetting transistor, causing current leakage and abnormal output due to the direct reset by a low voltage signal.
Innovation Solution
The driving circuitry incorporates a first resetting circuitry and a first isolation circuitry to control clock signals, ensuring the potential at the control node is reset and coupled to the node under specific clock signal control, thereby preventing current leakage and maintaining stable output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a low voltage signal is used to directly reset the transistor, then the resetting operation is simple and fast, but the transistor is cut off incompletely due to negative drift in threshold voltage, causing current leakage
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate electrode of the resetting transistor to a high voltage level before the reset operation. This preliminary charging ensures that when the low voltage reset signal is applied, the transistor can be completely turned off despite threshold voltage negative drift, preventing current leakage while maintaining fast reset timing
2Reliability
If a high voltage signal is used to reset the transistor, then the transistor can be completely cut off, but the circuit becomes more complex and energy consumption increases
Solution Approach 1:
The patent employs periodic action by using clock signals to periodically charge and discharge capacitors that control the gate voltage of the resetting transistor. This periodic charging mechanism ensures complete transistor cutoff during reset phases while using standard low voltage levels, avoiding the need for continuously complex high voltage generation circuits
Solution Approach 2:
The patent introduces intermediary elements (capacitors and clock signal circuits) that mediate between the low voltage reset signal and the transistor gate. These intermediaries temporarily store and release voltage to ensure complete transistor cutoff without requiring the main circuit to handle high voltages directly, thus maintaining circuit simplicity
3Reliability
If a high voltage signal is used to reset the transistor, then the transistor can be completely cut off, but energy consumption increases
Solution Approach 1:
The patent uses periodic clock signals to charge capacitors only when needed for transistor cutoff, rather than maintaining continuous high voltage. This periodic charging approach ensures complete transistor isolation when required while minimizing energy consumption during non-reset phases, as the capacitors discharge and the circuit operates at lower voltages
Data Source
AI summary
The present disclosure provides a driving circuitry, a driving method, a display substrate and a display device. The driving circuitry includes a driving output circuitry, a first resetting circuitry and a first isolation circuitry. The driving output circuitry is configured to control a driving signal output end to be electrically coupled to a first voltage line or a first clock signal line under the control of a potential at a first node. The first resetting circuitry is configured to control a first clock signal line to write a first clock signal into a first control node under the control of a first resetting signal. The first isolation circuitry is configured to control the first control node to be electrically coupled to the first node under the control of a second clock signal.