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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates finer patterns and three-dimensional channel structures to overcome limitations in operating characteristics due to size reductions in planar metal oxide semiconductor FETs.
Innovation Solution
A semiconductor device with a multi-bridge channel FET structure featuring a gate-all-around configuration, including a substrate with active regions, gate electrodes, channel layers, source/drain regions, and air gap regions, where the gate electrode layers have varying thicknesses to optimize electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar metal oxide semiconductor FETs are reduced in size to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional channel structures to three-dimensional vertical channel structures. The channel extends vertically through multiple layers with gate electrodes wrapping around from all directions, creating a gate-all-around configuration that provides superior electrostatic control while maintaining small footprint area for high integration density.
Solution Approach 2:
The gate electrode structure implements nesting by having inner gate electrodes positioned within outer gate electrodes, with multiple gate layers wrapped around the vertical channel in concentric configurations. This nested gate-all-around structure enables enhanced control over the channel while maintaining compact dimensions.
2Ease of manufacture
If uniform thickness electrode layers are used, then manufacturing is simplified, but electrical characteristics cannot be optimized
Solution Approach 1:
The electrode layers are designed with non-uniform thickness where specific regions have different thickness values to optimize local electrical characteristics. For example, gate electrode layers have varying thickness in different vertical and horizontal positions to control threshold voltage and electrical performance in specific device regions while maintaining overall structural integrity.
Data Source
AI summary
A semiconductor device includes: a substrate including an active region extending in a first direction; a gate electrode extending in a second direction and intersecting the active region, the gate electrode including first electrode layer(s) and a second electrode layer; channel layers spaced apart from each other in a third direction and at least partially surrounded by the gate electrode; source/drain regions, with at least one source/drain region on each side of the gate electrode and electrically connected to the channel layers; and air gap regions in the second electrode layer between the channel layers and between a lowermost channel layer and the active region in the third direction. The first electrode layer(s) or the second electrode layer has a first thickness between adjacent ones of the channel layers in the third direction, and has a second thickness greater than the first thickness on side surfaces of the channel layers.