Nanoinformatics TRIZ Cases
- Stacked GAA Channels with Anti-Punch-Through Dopant Control
A prebake, diffusion-blocking layer, and epitaxial channel stack help retain dopants and suppress parasitic mesa leakage in GAA devices.
- Nanostructure Transistor Gates Without Barrier Layer Deposition
Removing barrier layers from confined gate-stack regions simplifies deposition, reduces defects, and preserves transistor electrical characteristics.
- Isotopically Depleted Semiconductor Structures for Stable Spin Qubits
Silicon-29 can cause spin-qubit decoherence; epitaxy and annealing create a depleted layer for greater spin-state stability.
- Trimmed-Channel Semiconductor Device for Reduced Gate Defects
Scaled semiconductor features can cause shorts, voids, and etch residues; sacrificial dielectric spacers and trimmed fins improve gate insulation.
- Super-Hydrophobic Graphene Reference Electrode for Miniaturized Sensing
Fluorinated or silanized graphene forms a super-hydrophobic layer, helping miniaturize sensing electrodes and simplify integration.
- Self-Aligned Wraparound Gates for Tighter GAA Device Spacing
Dielectric-fin alignment guides wraparound metal-gate etching around semiconductor layers, enabling tighter spacing with fewer lithography steps.
- Transistor Source/Drain Carbon Liners for Dopant Diffusion Control
Scaled transistors use epitaxial carbon-rich liner layers to limit dopant out-diffusion and preserve channel mobility.
- SRAM Cell Layout Using Back-Side Routing to Reduce Interconnect Complexity
GAA SRAM arrays use front-side word lines and under-cell back-side bit-line routing to reduce routing resource consumption and improve cell scalability.
- Gate Structures with Barrier-Metal Tuning for FET Threshold Voltages
Varying barrier-metal thickness enables different FET threshold voltages while keeping work function metal layer thicknesses similar.
- GAA and Comb-Nanosheet Transistor Integration for Density Tuning
Regional fin spacing combines performance-focused GAA nanosheets with denser comb-nanosheets on one substrate, using STI isolation.
- Nanosheet Channel Structures with Thin Silicon Work-Function Layers
Aluminum-containing work-function layers can hinder transistor scaling; a thinner silicon-containing layer preserves band-edge work function and gate control.
- Segmented Metal Gate Stacks for Compact Nanostructure FETs
Tight nanostructure spacing limits threshold-voltage tuning and raises resistance; segmented gate layers address both constraints.
- Semiconductor Reflow Layers for Reliable Stacked-Channel MOSFETs
A graded SiGe reflow buffer helps prevent stacking faults and reduce channel resistance in vertically stacked MOS-FETs.
- Tapered Gate-All-Around Structure for Bottom-Gate Wiring Access
Variable channel widths narrow selected regions for bottom-gate wiring while preserving wide sections for drive-strength in stacked transistors.
- Low-K Gate Spacers for Strained PMOS Gate-All-Around Transistors
Low-k spacers formed by oxidizing source/drain inner walls reduce parasitic capacitance and support strain retention in PMOS nanowire channels.
- GAA Nanostructure FET Epitaxial Stress for Lower Channel Resistance
Epitaxial source/drain regions exert stress on nanostructures, improving electrical characteristics while reducing channel resistance.
- Forksheet Transistor Antifuse Memory for Compact OTP Integration
See how forksheet transistors implement antifuse one-time programming while sharing structures to reduce circuit area and improve integration.
- Multi-Gate Devices With Dielectric Fins for Uniform Inner Spacers
Dielectric fins and sacrificial cladding reserve metal-gate space while removal before spacer formation improves inner-spacer uniformity.
- Multigate Device Bottom Isolation for Leakage Control
An insulation layer between the gate stack and substrate suppresses parasitic transistors, leakage current, and capacitance in multigate devices.
- Lateral Source-Drain Epitaxy Confinement for Cell-Height Scaling
A mold confines lateral source-drain epitaxial growth in nanoribbon transistors, easing lithographic scaling limits and supporting higher device density.
- Hybrid FinFET–GAA Channel for High Drive and Steep Subthreshold Swing
A lower fin and upper nanowire or nanosheet channel combine FinFET and GAA behavior to improve drive and reduce leakage.
- Display Device Sensing Layer for External Input Detection
A sensing layer enables the display device to detect an external input device, focusing the case on external-input sensing.
- Semiconductor Devices With Dummy-Fin Gate Segmentation
Dummy fins segment gate structures before formation, preventing gate-contact shorts caused by profile variation and supporting flexible circuit layouts.