Segmented Metal Gate Stacks for Compact Nanostructure FETs
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Solution Overview
Problem
The fabrication of metal gate stacks in multi-gate field-effect transistors, such as nanostructure FETs, is challenged by tightened separation distances between vertically stacked nanostructures, limiting flexibility in tuning threshold voltage and increasing resistance due to reduced thickness of low-resistance metal fill layers.
Innovation Solution
A metal gate stack design that includes a gate dielectric layer wrapping around channel layers, work-function metal layers filling the space between these layers, and a bulk conductive metal fill layer on top, allowing for independent composition tuning of different FET types and reducing resistance without enlarging separation distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the separation distance between vertically stacked nanostructures is reduced, then the chip footprint is reduced, but the flexibility in tuning threshold voltage is limited and resistance increases
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a gate dielectric layer wrapping around channel layers, work-function metal layers filling spaces between channel layers, and a bulk conductive metal fill layer on top. This segmentation allows independent optimization of each layer's thickness and composition, enabling threshold voltage tuning without increasing separation distances between nanostructures.
Solution Approach 2:
The gate stack employs composite material structures combining different metal layers with distinct properties. The work-function metal layers provide threshold voltage control through their specific work functions, while the bulk conductive metal fill layer provides low resistance. This composite approach allows simultaneous optimization of electrical control and conductivity without enlarging the device footprint.
2Length of stationary object
If the thickness of low-resistance metal fill layers is reduced, then the separation distance between nanostructures is reduced, but resistance increases
Solution Approach 1:
Different regions of the gate stack are assigned different material qualities: work-function metal layers are positioned where electrical control is needed, while bulk conductive metal fill is placed in regions where low resistance is critical. This local optimization allows the metal fill to maintain adequate thickness for low resistance while keeping overall separation distances small.
Solution Approach 2:
The composite gate stack structure combines work-function metal layers with a bulk conductive metal fill layer. The bulk conductive metal fill layer is specifically designed with sufficient thickness to provide low resistance pathways, while the overall gate stack geometry maintains compact separation distances between vertically stacked nanostructures.
3Adaptability or versatility
If a complex metal gate stack structure is implemented, then flexibility in tuning threshold voltage improves, but device complexity increases
Solution Approach 1:
The gate stack is divided into distinct functional segments: gate dielectric layer, work-function metal layers, and bulk conductive metal fill layer. Each segment has a specific function that can be independently optimized, allowing threshold voltage tuning through material selection and thickness control without requiring complex three-dimensional configurations.
Solution Approach 2:
The metal gate stack structure serves multiple functions simultaneously: the gate dielectric provides electrical isolation, work-function metal layers provide threshold voltage control, and the bulk conductive metal fill provides low resistance. This multi-functionality is achieved through a relatively simple layered structure that can be applied universally to different multi-gate transistor configurations.
Data Source
AI summary
A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.