Trimmed-Channel Semiconductor Device for Reduced Gate Defects
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Solution Overview
Problem
As semiconductor device dimensions shrink, manufacturing process deviations lead to increased likelihood of short circuits and open circuits due to pattern shifts, uneven material deposition, and etch residues, which affect dielectric breakdown and conductive material bridges.
Innovation Solution
The formation of an active area spacer along the sidewall of the active area, using a sacrificial dielectric layer, and trimming isolating fins to reduce the presence of stringers and voids, along with adjusting manufacturing processes to enhance dielectric material quality and deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are shrunk to increase integration density, then productivity and device capacity improve, but manufacturing precision deteriorates due to increased sensitivity to process deviations
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and spacer before the final gate electrode deposition. The mandrel is positioned preliminarily to define the channel region, and the spacer is formed around it to create precise spacing. This preliminary structuring ensures accurate feature placement even when device dimensions are shrunk, compensating for potential alignment errors in subsequent processing steps.
Solution Approach 2:
The patent uses an intermediary mandrel structure that is eventually removed after transferring its pattern to the final device features. The mandrel acts as a temporary mediator that enables precise feature formation through spacer deposition, then is discarded. This intermediary approach allows for high precision in the final structure without requiring equally high precision in all processing steps.
2Device complexity
If conventional manufacturing processes are used for scaled devices, then process simplicity is maintained, but reliability deteriorates due to increased short circuits and open circuits from process deviations
Solution Approach 1:
The patent segments the gate formation process into distinct stages: mandrel formation, spacer deposition, mandrel removal, and gate electrode formation. This segmentation allows each step to be optimized independently for reliability while maintaining overall process manageability. The spacer acts as a separate protective element that prevents short circuits during etching, and the mandrel provides a separate template for precise feature definition.
Solution Approach 2:
The patent applies beforehand cushioning by forming the spacer structure in advance to protect against potential short circuits during subsequent etching processes. The spacer acts as a protective buffer that prevents conductive material bridges even when etch residues or pattern shifts occur. This protective structure is built beforehand to cushion against manufacturing variations that would otherwise cause device failure.
3Ease of manufacture
If uniform dielectric material deposition is performed, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to stringers and voids in gate electrodes
Solution Approach 1:
The patent applies local quality by creating non-uniform spacer thickness through selective etching of the mandrel. The spacer is formed with varying thickness in different regions - thicker in some areas and thinner in others - based on the local mandrel geometry. This local variation in spacer quality allows for precise control of gate electrode dimensions and prevents stringer formation, while the overall deposition process remains relatively simple and uniform.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces short circuits and voids in gate electrodes, improving transistor performance and reliability by enhancing dielectric insulation and reducing manufacturing defects.
Implementation Method 1
A liquid etch process is performed to remove a portion of the sacrificial dielectric material in the channel trim zone to expose the channel
Implementation Method 2
depositing a gate electrode material against the first fin region and the gate dielectric in the channel region
Data Source
AI summary
A semiconductor device includes an active area extending in a first direction over a substrate, the active area including at least one conductive path extending from a source region, through a channel region, to a drain region; and a gate dielectric on a surface of the at least one conductive path in the channel region. The semiconductor device also includes an isolating fin at a first side of the active area, the isolating fin having a first fin region having a first fin width adjacent to the source region, a second fin region having a second fin width adjacent to the channel region, and a third fin region having the first fin width adjacent to the drain region; and a gate electrode against the gate dielectric in the channel region.