Multigate Device Bottom Isolation for Leakage Control
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Solution Overview
Problem
Multigate devices, particularly gate-all-around (GAA) FETs, face significant leakage current issues due to parasitic transistors forming between the gate stack and the elevated substrate, which worsen as IC technology nodes scale, leading to drain-induced-barrier-lowering and increased parasitic capacitance, and existing solutions like reducing mesa dimensions or using semiconductor-on-insulator substrates are either ineffective or costly.
Innovation Solution
Implementing a bottom isolation technique with an insulation layer between the gate stack and the semiconductor mesa, using a dielectric material like silicon nitride, which physically and electrically isolates the gate stack from the substrate, reducing leakage current and parasitic capacitance while maintaining device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multigate devices are scaled down to improve gate control and reduce short-channel effects, then device density and integration are improved, but leakage current increases due to parasitic transistors forming between the gate stack and elevated substrate
Solution Approach 1:
An insulation layer is introduced as an intermediary element between the gate stack and the elevated substrate (mesa). This insulation layer acts as a mediator that physically and electrically separates the gate stack from the substrate, preventing the formation of parasitic transistors and the associated leakage current paths while allowing the device to maintain its scaled-down dimensions for high density
Solution Approach 2:
The device structure is segmented by introducing the insulation layer that divides the space between the gate stack and substrate into distinct regions. This segmentation creates electrical isolation zones that block leakage current paths without affecting the functional regions of the multigate device, enabling simultaneous achievement of high density and low leakage
2Object-generated harmful factors
If mesa dimensions are reduced to suppress leakage current, then parasitic transistor formation is reduced, but device performance and gate control are degraded
Solution Approach 1:
The insulation layer serves as a mediator that enables leakage current suppression without requiring reduction of mesa dimensions. By placing the insulation layer between the gate stack and mesa, the patent achieves electrical isolation while maintaining larger mesa sizes that support better device performance and gate control
Solution Approach 2:
The patent changes the electrical parameters of the structure by introducing the insulation layer with specific dielectric properties. This parameter change enables the system to achieve low leakage current while maintaining the physical dimensions and electrical characteristics of the mesa that are necessary for optimal device performance
3Object-generated harmful factors
If semiconductor-on-insulator substrates are used to reduce leakage current, then parasitic transistor formation is suppressed, but manufacturing cost increases
Solution Approach 1:
Instead of using expensive semiconductor-on-insulator substrates that provide global insulation, the patent applies local quality by introducing insulation only in the specific region where it is needed - between the gate stack and the elevated substrate. This localized approach suppresses parasitic transistor formation at the critical interface while avoiding the high cost of complete substrate replacement
Solution Approach 2:
The patent uses a cost-effective insulation layer deposited directly on the existing substrate rather than requiring expensive semiconductor-on-insulator substrates. This approach uses cheaper materials and processes to achieve the same functional goal of leakage current suppression, making the solution economically viable for manufacturing
4Productivity
If gate stack is placed close to substrate to maintain device dimensions, then device scaling is achieved, but parasitic capacitance increases
Solution Approach 1:
The insulation layer acts as an intermediary that increases the electrical distance between the gate stack and substrate without significantly increasing the physical device dimensions. This mediator reduces parasitic capacitance by providing electrical isolation while allowing the device to maintain its scaled dimensions for high productivity
Solution Approach 2:
The patent addresses the capacitance issue by adding insulation in the vertical dimension between the gate stack and substrate, rather than increasing lateral dimensions. This dimensional approach reduces parasitic capacitance while maintaining the device's scaled footprint and integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insulation layer effectively suppresses leakage current and parasitic capacitance, enhancing off-state control and overall performance of GAA devices without degrading other electrical characteristics, allowing independent design of channel and gate stack dimensions.
Implementation Method 1
an insulation layer between the gate stack and the semiconductor mesa, using a dielectric material like silicon nitride, which physically and electrically isolates the gate stack from the substrate
Implementation Method 2
an insulation layer between the gate stack and the semiconductor mesa, using a dielectric material like silicon nitride, which physically and electrically isolates the gate stack from the substrate
Data Source
AI summary
An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.