Low-K Gate Spacers for Strained PMOS Gate-All-Around Transistors
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Solution Overview
Problem
Existing gate spacers in gate-all-around transistors, particularly for PMOS devices, suffer from high dielectric constant and parasitic capacitance, leading to degraded performance due to loss of strain in nanowires and defects in source and drain regions, which affects hole mobility and switching performance.
Innovation Solution
Forming gate spacers by oxidizing or condensation annealing the inner walls of source and drain regions before epitaxial growth of source and drain regions, using materials like SiGe to create low-k gate spacers with a dielectric constant of 3.9 to 4.2, ensuring strain is introduced and defects are minimized.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate spacers with high dielectric constant are used, then the gate spacer provides adequate mechanical support and isolation, but parasitic capacitance increases and strain is lost in nanowires
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate spacer material from conventional high-k materials to low-k materials (such as silicon oxide with k≈3.9 or silicon nitride with k≈4.2). This parameter change directly reduces parasitic capacitance between the gate spacer and channel, thereby reducing the harmful electrostatic coupling that causes strain loss in the nanowire channel.
Solution Approach 2:
The patent employs composite material structures where the gate spacer is formed from specific low-k materials that combine mechanical support properties with low dielectric constant. The gate spacer may be composed of silicon oxide, silicon nitride, or other low-k materials that provide both structural integrity and reduced parasitic capacitance, creating a composite solution that addresses both mechanical support and electrical isolation requirements.
2Reliability
If gate spacers are formed before epitaxial growth, then strain can be introduced in nanowires, but defects may occur in source and drain regions
Solution Approach 1:
The patent performs preliminary formation of the gate spacer structure before epitaxial growth of the channel and source/drain regions. This preliminary action establishes the low-k gate spacer in place, which then serves as a template and strain-inducing structure during subsequent epitaxial growth. The pre-formed gate spacer ensures that strain is properly introduced into the nanowire channel during growth, improving hole mobility for PMOS devices.
Solution Approach 2:
The patent applies local quality control by ensuring that the low-k gate spacer material is specifically positioned and configured to induce strain only in the channel region where it is needed. The gate spacer's low dielectric constant and specific geometry create localized strain fields that enhance hole mobility in the channel without adversely affecting the source and drain regions, thereby maintaining manufacturing precision while improving device performance.
3Object-generated harmful factors
If low-k gate spacers are used, then parasitic capacitance is reduced and hole mobility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the gate spacer formation step from the conventional high-k material deposition process and replaces it with low-k material deposition and selective removal techniques. By taking out the harmful high dielectric constant property and replacing it with low-k materials, the patent reduces parasitic capacitance. The fabrication process uses selective etching and deposition to create the low-k gate spacer structure, which may involve removing portions of previously deposited materials and replacing them with low-k materials such as silicon oxide or silicon nitride.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-k gate spacers reduce parasitic capacitance, enhance hole mobility, and improve switching performance, especially at high frequencies, by allowing defect-free epitaxial growth and lattice matching with nanowires.
Implementation Method 1
forming gate spacers by oxidizing or condensation annealing the inner walls of source and drain regions
Implementation Method 2
forming gate spacers by oxidizing or condensation annealing the inner walls of source and drain regions
Data Source
AI summary
A gate-all-around transistor device includes a body including a semiconductor material, and a gate structure at least in part wrapped around the body. The gate structure includes a gate electrode and a gate dielectric between the body and the gate electrode. The body is between a source region and a drain region. A first spacer is between the source region and the gate electrode, and a second spacer is between the drain region and the gate electrode. In an example, the first and second spacers include germanium and oxygen. The body can be, for instance, a nanoribbon, nanosheet, or nanowire.