Tapered Gate-All-Around Structure for Bottom-Gate Wiring Access
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Solution Overview
Problem
Existing semiconductor fabrication technologies face challenges in scaling transistors beyond single digit nanometer nodes due to limitations in wiring access to bottom gates and maintaining wide device width for high drive-strength in three-dimensional circuits.
Innovation Solution
The use of tapered devices and spacer-based integration flows to selectively narrow device width where access to bottom gates is needed, allowing for increased connectivity and drive-strength while maintaining transistor density through variable channel width transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If device width is increased to maintain high drive-strength, then drive-strength is improved, but wiring access to bottom gates becomes difficult
Solution Approach 1:
The device width is segmented into different regions: a first device region with a first width optimized for drive-strength, and a second device region with a second width optimized for wiring access. This segmentation allows each region to fulfill its specific function without compromising the other.
Solution Approach 2:
Different portions of the device are assigned different widths based on local requirements. The first device region has a larger width to provide high drive-strength, while the second device region has a smaller width to enable wiring access to bottom gates. This local quality variation resolves the contradiction between overall device performance and local accessibility.
2Productivity
If transistor density is increased through vertical stacking, then transistor density is improved, but complexity of gate separation increases
Solution Approach 1:
The vertically stacked transistor structure is segmented into an upper transistor and a lower transistor, each with separate gates. The gate separation structure is designed to selectively separate these transistors, allowing independent control while maintaining vertical stacking for high density.
Solution Approach 2:
A gate separation structure acts as an intermediary element between the upper and lower transistors. This structure enables the separation of gates in the vertically stacked configuration, facilitating independent gate control without requiring complete structural separation, thus managing complexity while maintaining density.
3Ease of manufacture
If single exposure EUV processing is used, then manufacturing simplicity is maintained, but ability to achieve tight contacted poly pitch decreases
Solution Approach 1:
The device structure is segmented into regions with different widths, which can be formed using single exposure EUV processing. The first device region with larger width and second device region with smaller width can be patterned in a single exposure, achieving the desired structure without requiring multiple exposures or complex processing steps.
Data Source
AI summary
Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.