GAA and Comb-Nanosheet Transistor Integration for Density Tuning
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Solution Overview
Problem
Current chip fabrication schemes do not co-integrate gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, limiting the scaling benefits and forcing fabricators to choose one nanosheet type over the other.
Innovation Solution
A method for co-integrating GAA nanosheets and comb-nanosheets on the same chip by forming GAA nanosheet devices in one region and comb-nanosheet devices in another, using a shallow trench isolation (STI) liner as a dielectric pillar, and employing replacement metal gate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA nanosheet devices are formed with larger fin spacing distance, then device performance is improved, but device density is reduced
Solution Approach 1:
The patent applies local quality by implementing different fin spacing distances in different regions of the semiconductor device. The first region contains GAA nanosheet devices with a first fin spacing distance optimized for performance, while the second region contains comb-nanosheet devices with a second fin spacing distance optimized for density. This allows each region to be optimized independently for its specific function.
2Area of moving object
If comb-nanosheet devices are used to increase device density, then area efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor device into distinct regions, with the first region containing GAA nanosheet devices and the second region containing comb-nanosheet devices. This segmentation allows each device type to be fabricated using its optimized process flow while maintaining overall device functionality. The shallow trench isolation structure further segments the substrate to enable independent processing of each region.
Solution Approach 2:
The patent employs a universal approach by using a common shallow trench isolation structure and replacement metal gate process that can accommodate both GAA nanosheet and comb-nanosheet device formations. This multi-functional process framework reduces the overall manufacturing complexity despite the presence of two different nanosheet architectures.
3Adaptability or versatility
If different nanosheet types are integrated on the same chip, then functionality is improved, but fabrication process complexity increases
Solution Approach 1:
The patent implements different nanosheet types in different regions with optimized local characteristics. The first region uses GAA nanosheets for performance-critical functions, while the second region uses comb-nanosheets for density-critical functions. This localized optimization enables the chip to achieve multiple functionality goals without requiring uniform structure throughout.
Solution Approach 2:
The shallow trench isolation structure serves as an intermediary element that facilitates the co-integration of different nanosheet types. It provides electrical isolation between regions while maintaining a common fabrication framework, thereby enabling functional diversity without proportionally increasing fabrication complexity.
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.