Semiconductor Reflow Layers for Reliable Stacked-Channel MOSFETs
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Solution Overview
Problem
The scaling-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices degrades operational properties, necessitating improved reliability in semiconductor devices with small pattern sizes and reduced design rules.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with a source/drain pattern comprising a buffer layer of silicon germanium (SiGe) and a main layer, where the buffer layer has a lower germanium concentration than the semiconductor layer, and a gate electrode with protruding and concave portions, along with a specific thickness ratio, enhances reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to achieve small pattern size and reduced design rule, then device density and integration are improved, but operational properties and reliability are degraded
Solution Approach 1:
The buffer layer is designed with non-uniform germanium concentration distribution, where the germanium concentration varies from the interface with the semiconductor pattern to the surface. This local quality variation allows the buffer layer to provide different functional characteristics at different depths: strong lattice matching at the interface to prevent stacking faults, and gradual composition transition toward the surface to manage thermal expansion and stress effects, thereby maintaining reliability in scaled-down devices
Solution Approach 2:
The patent changes the germanium concentration parameter through the thickness of the buffer layer, creating a gradient structure. By controlling the germanium concentration to decrease from the semiconductor pattern interface toward the surface, and by optimizing the buffer layer thickness (e.g., 2-10 nm), the structure achieves both stacking fault prevention and thermal stress management, resolving the reliability issue in scaled MOS-FETs
2Reliability
If buffer layer thickness is increased to prevent stacking faults, then reliability is improved, but channel resistance increases and device performance degrades
Solution Approach 1:
The buffer layer employs local quality variation through its thickness, with higher germanium concentration near the semiconductor pattern interface to maximize stacking fault prevention, and lower germanium concentration toward the surface to minimize thermal expansion mismatch and reduce channel resistance. This spatial variation of material composition allows simultaneous optimization of reliability and electrical performance
Solution Approach 2:
The germanium concentration parameter is varied continuously or in steps through the buffer layer thickness. By controlling this composition gradient and the overall buffer layer thickness within optimal ranges (e.g., 2-10 nm), the structure achieves effective stacking fault suppression without excessive resistance increase, resolving the trade-off between reliability and power performance
3Reliability
If germanium concentration in buffer layer is increased to prevent stacking faults, then reliability is improved, but lattice mismatch and thermal expansion differences increase causing operational degradation
Solution Approach 1:
The buffer layer is designed with spatially varying germanium concentration, where the concentration is highest at the interface with the semiconductor pattern to maximize stacking fault prevention, and gradually decreases toward the surface. This gradient structure ensures strong lattice matching where needed while minimizing thermal expansion mismatch and compositional strain in the upper regions, thereby reducing harmful effects on device operation
Solution Approach 2:
The germanium concentration parameter is optimized to vary through the buffer layer thickness, balancing the competing requirements: high concentration near the interface for stacking fault suppression, and lower concentration at the surface to minimize thermal expansion differences and lattice mismatch. This parameter optimization resolves the contradiction between reliability improvement and harmful factor reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability and operational performance of semiconductor devices by preventing stacking faults and reducing channel resistance, enabling higher channel sizes and faster operation.
Implementation Method 1
the buffer layer includes a first semiconductor layer and a first reflow layer disposed on the first semiconductor layer. A germanium concentration of the first reflow layer is less than a germanium concentration of the first semiconductor layer
Implementation Method 2
The gate electrode includes a plurality of portions that are respectively interposed between the plurality of semiconductor patterns
Implementation Method 3
A germanium concentration of the first reflow layer is less than a germanium concentration of the first semiconductor layer
Data Source
AI summary
A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.