Nanostructure Transistor Gates Without Barrier Layer Deposition
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in depositing barrier layers in small spaces of advanced semiconductor nodes, leading to manufacturing defects and thickness variations in work function metal layers that affect transistor performance.
Innovation Solution
Omitting barrier layers in gate stacks and allowing work function metal layers to merge in certain areas, improving manufacturing ease without significantly impacting electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If barrier layers are deposited in small spaces of advanced semiconductor nodes, then manufacturing precision is improved, but device complexity increases and manufacturing defects occur
Solution Approach 1:
The patent removes the barrier layer from the gate stack structure entirely, extracting the problematic component that caused deposition difficulties in small spaces. This eliminates the need to deposit barrier layers in confined areas, resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The work function metal layer is segmented into multiple sections (first work function metal layer and second work function metal layer) that can be deposited separately and merged in between nanostructures. This segmentation allows for easier deposition in small spaces compared to a continuous barrier layer.
2Manufacturing precision
If barrier layers are deposited in small spaces, then manufacturing precision is improved, but productivity decreases due to manufacturing defects
Solution Approach 1:
By removing the barrier layer from the process, the patent eliminates the source of manufacturing defects that reduced productivity. The simplified process flows without the problematic barrier layer deposition step, improving manufacturing efficiency while maintaining necessary precision through alternative means.
Solution Approach 2:
The work function metal layers are deposited with preliminary thickness control and merging design, ensuring proper electrical performance is achieved before final assembly. This preliminary planning eliminates the need for rework and defects associated with barrier layer deposition.
3Ease of manufacture
If work function metal layers are kept separate, then manufacturing ease is improved, but electrical performance deteriorates due to thickness variations
Solution Approach 1:
The patent designs the work function metal layers to merge in between the nanostructures, combining separate deposited layers into a continuous functional structure. This merging ensures proper electrical performance and threshold voltage control while maintaining the manufacturing ease of separate deposition steps.
Solution Approach 2:
The work function metal layers have different properties in different locations: they are separate and controllable during deposition, then merge in the critical between-nanostructure regions where electrical continuity is needed. This local variation in structure quality achieves both manufacturing ease and electrical reliability.
Data Source
AI summary
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.